Application Note
15 of 19
001-87564 Rev.*D
2021-06-01
A Design Guide to SPI F-
RAM™ Processor Companion
- FM33256B
Pseudo Code Examples
r e s t r i c t e d
10.5
Read Event Counters
/**************************
Read Event Counters **************************/
// Step #1 Set RC bit which takes snapshot of both counter registers
data[0] = 0x09;
// Data for setting the RC bit and keeps CP=1
WRITE_RTC (0x0D,
// Sets the address pointer to Register 0Dh
data,
// Writes data 0x09 which sets the R bit
0x01);
// Number of bytes to be written
// Step #2 Read Event Counter
READ_RTC (0x0E,
// Sets the address pointer to Register 0Dh
data,
// Data buffer to read RTC registers
0x02);
// Number of bytes to be read
// data buffer contains the following
// 0x1A
–
CounterByte0 reads out LSB 0x1A (decimal 26)
// 0x00
–
CounterByte1 reads out MSB 0x00
// Step #3 Clear RC bit
data[0] = 0x01;
// data=0x01 clears the RC bit
WRITE_RTC (0x0D,
// Sets the address pointer to Register 0Ch
data,
//
Data=0x01 clears the RC bit and keeps C1P=1
0x01);
// Number of bytes to be written
