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2020-5-22
UG2020-11 REF-Vacuum-C101-2ED User Guide
4.1
Internal block diagram
Figure 4 illustrates the internal block diagram of the 2ED2304S06F.
VCC
LO
COM
UV-
DETECT
DELAY
LIN
VS
HO
VB
BIAS NETWORK - VB
COMPA
RATOR
HV LEVEL-SHIFTER
+ REVERSE-DIODE
LATCH
UV-
DETECT
Gate-
Drive
HIN
GND / PGND
LEVEL-
SHIFTER
Gate-
Drive
In
te
rl
o
c
k
,
D
e
a
d
ti
m
e
,
F
ilt
e
r
ti
m
e
s
,
P
ro
p
a
g
a
ti
o
n
d
e
la
y
Boostrap diode
VCC
VCC
VCC
Figure 4
Block diagram of 2ED2304
The Schmitt trigger logic inputs are compatible with standard CMOS or LSTTL logic down to 3.3 V. The output
drivers feature a high-pulse current buffer stage designed for minimum driver cross-conduction. The floating
channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration, which
operates up to 650 V.
Additionally, the offline clamping function provides an inherent protection of the parasitic turn-on by floating
gate conditions when the IC is not power-supplied.
2ED2304S06F is DSO-8 package; the pin definition is the same as IRS2304, as shown in Figure 5.
Figure 5
2ED2304S06F lead assignments PG-DSO-8 (top view)
