Document Number: 002-14826 Rev. *G
Page 18 of 65
PRELIMINARY
CYW43903
5.4 PWM
The CYW43903
provides up to six independent pulse width modulation (PWM) channels. The following features apply to the PWM
channels:
■
Each channel is a square wave generator with a programmable duty cycle.
■
Each channel generates its duty cycle by dividing down the input clock.
■
Both the high and low duration of the duty cycle can be divided down independently by a 16-bit divider register.
■
Each channel can work independently or update simultaneously.
■
Pairs of PWM outputs can be inverted for devices that need a differential output.
■
Continuous or single pulses can be generated.
■
The input clock can either be a high-speed clock from a PLL channel or a lower speed clock at the crystal frequency.
5.5 SPI Flash
The SPI flash interface supports the following features:
■
A SPI-compatible serial bus.
■
An 80 MHz (maximum) clock frequency.
■
Increased Throughput to 40 MBps in Quad-mode or upto 10 MBps in single Mode
3
.
■
Support for either ×1 or ×4 addresses with ×4 data.
■
3-bytes and 4-byte addressing modes.
■
A configurable dummy-cycle count that is programmable from 1 to 15.
■
Programmable instructions output to serial flash.
■
An option to change the sampling edge from rising-edge to falling-edge for read-back data when in high-speed mode.
5.6 UART
A high-speed 4-wire CTS/RTS UART interface can be enabled by software and has dedicated pins. Provided primarily for debugging
during development, this UART enables the CYW43903 to operate as RS-232 data termination equipment (DTE) for exchanging and
managing data with other serial devices. It is compatible with the industry standard 16550 UART and provides a FIFO size of 64 × 8
in each direction.
There are two low-speed UART interfaces on
the CYW43903. Each
functions as a standard 2-wire UART. They are also enabled as
alternate functions on GPIOs and can be enabled independently of the 4-wire fast UART.
Note:
The high-speed, 4-wire UART interface is identified as UART0 in this document and in reference schematics. The two low-
speed, 2-wire UART interfaces are identified as UART1 and UART2 in this document and in the reference schematics.
3. Note that the clock needs to be constrained to ~26.67MHz for reliable operation at high operating temperatures. The throughput of the SPI Flash block is
therefore restricted to ~13 MBps for Quad mode and ~3 MBps for single mode.
