User Guide
35 of 67
002-32601 Rev. *C
2021-12-02
EZ-
PD™ PMG1 MCU prototyping kits guide
CY7110/CY7111/CY7112/CY7113
EZ-
PD™ PMG1 prototyping kit system design
3.4
KitProg3 (PSoC™ 5LP MCU)
An onboard PSoC
™
5LP MCU (CY8C5868LTI-LP039)-based KitProg3 module is used to program and debug the
EZ-
PD™
PMG1 microcontroller.
Figure 29
PSoC
™
5LP MCU device
The PSoC
™
5LP MCU device interfaces with a PC through a Type-C USB connector (J1), and functions as a
bridge between the PC and EZ-
PD™
PMG1 MCU devices over SWD, I2C, and UART interfaces. The KitProg3
module gets power through the J1 port and receives and transmits data between the host PC through D+/D-
signals. The programming/debugging module can access the EZ-
PD™
PMG1 MCU device in programming or
debugging mode via the SWD header. In addition to being an onboard programmer, the KitProg3 functions as
an interface for the USB-I2C and USB-UART bridges.
The USB-Serial pins of PSoC
™
5LP MCU are hard-wired to the I2C pins of the EZ-
PD™
PMG1 MCU, and these pins
are also available on the KitProg3 headers (J3 and J4).
The USB-UART bridge functionality is enabled by default by hard-wired connections of the UART lines between
KitProg3 and EZ-
PD™
PMG1 MCU. However, the following older revisions of the PMG1 kit boards require manual
external wire connection:
•
CY7110 board revision 3 or lower
•
CY7111 board revision 2 or lower
•
CY7112 board revision 2 or lower
•
CY7113 board revision 3 or lower
P5LP2_0
P5LP_SIO_VREF
P5LP1_2
KP_IO
P5LP1_4
P5LP_VDD
UART_RX
SAR Bypass
Capacitor
C36
1.0 uF
No Load
KP_DM
PSoC 5LP Power
SWDIO
P5LP_VDD
P5LP_VDD
P5LP_VDD
P5LP_VDD
UART_TX
I2C_SDA
UART_CTS
R37
22E
XRES
KP_CLK
P5LP_VCCD
P5LP_VDD
KP_VBUS_P
P5LP2_2
R41
0ohm
KP_CLK
SWDCLK
KP_DP
VTARG_MEAS
I2C_SCL
P5LP2_3
P5LP2_1
R38
22E
R10
100K
P5LP_VCCD
J2
1X5 Header
No Load
1
2
3
4
5
Del-Sig Bypass
Capacitor
KP_IO
P5LP2_4
PSoC 5LP based KitProg3
C5
1.0 uF
XRES
C1
1.0 uF
RESET
3,4
P5LP_VDD
USB_V_SENSE
U1
CY 8C5868LTI-LP039
P2[
3]
65
P2[
1]
63
P12[3]
47
P3[7]
37
P3[
5]
34
P3[
3]
32
P3[
1]
30
P15[3]
41
P15[2]
40
P1[
7]
19
P1[5]
16
P1[3]
14
P1[1]
12
VSSD
25
P15[
6]
D
+
22
P15[
7]
D
-
23
VC
C
D
26
P12[0]
38
P1[0]
11
P1[2]
13
P1[4]
15
P1[
6]
18
P3[
0]
29
P3[
2]
31
P3[
4]
33
P12[1]
39
P12[2]
46
P3[6]
36
P2[
0]
62
P2[
2]
64
P2[
4]
66
P2[6]
1
P0[0]
48
P0[2]
50
P0[
4]
53
P0[
6]
55
VD
D
D
59
VSSD
58
P0[
7]
56
P0[
5]
54
P0[3]
51
P0[1]
49
P2[7]
2
P2[
5]
68
P12[4]
3
P12[5]
4
VSSB
5
IND
6
VBOOST
7
VBAT
8
VSSD
9
XRES
10
VDDIO1
17
P12[
6]
20
P12[
7]
21
VD
D
D
24
P15[
0]
27
P15[
1]
28
VD
D
IO2
67
P15[
5]
61
P15[
4]
60
VC
C
D
57
VD
D
IO
52
VSSD
45
VDDA
44
VSSA
43
VCCA
42
VDDIO3
35
EPAD
H
