Infineon C513AO, Руководство пользователя

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Memory Organization
C513AO
User’s Manual 3-8 05.99
Table 3-2
Contents of the SFRs, SFRs in Numeric Order of Their Addresses
Addr Register Content
after
Reset
1)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
80
H
2)
P0 FF
H
.7 .6 .5 .4 .3 .2 .1 .0
81
H
SP 07
H
.7 .6 .5 .4 .3 .2 .1 .0
82
H
DPL 00
H
.7 .6 .5 .4 .3 .2 .1 .0
83
H
DPH 00
H
.7 .6 .5 .4 .3 .2 .1 .0
86
H
WDTREL 00
H
WDT
PSEL .6 .5 .4 .3 .2 .1 .0
87
H
PCON 0XX0-
0000
B
SMOD –
–
SD GF1 GF0 PDE IDLE
88
H
2)
TCON 00
H
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
88
H
3)
PCON1 0XXX-
XXXX
B
EWPD – – – – – – –
89
H
TMOD 00
H
GATE C/T M1 M0 GATE C/T M1 M0
8A
H
TL0 00
H
.7 .6 .5 .4 .3 .2 .1 .0
8B
H
TL1 00
H
.7 .6 .5 .4 .3 .2 .1 .0
8C
H
TH0 00
H
.7 .6 .5 .4 .3 .2 .1 .0
8D
H
TH1 00
H
.7 .6 .5 .4 .3 .2 .1 .0
90
H
2)
P1 FF
H
– – .SLS STO SRI SCLK T2EX T2
98
H
2)
SCON 00
H
SM0 SM1 SM2 REN TB8 RB8 TI RI
99
H
SBUF XX
H
.7 .6 .5 .4 .3 .2 .1 .0
A0
H
2)
P2 FF
H
.7 .6 .5 .4 .3 .2 .1 .0
A8
H
2)
IE 00
H
EA ESSC ET2 ES ET1 EX1 ET0 EX0
B0
H
2)
P3 FF
H
RD WR T1 T0 INT1 INT0 TxD RxD
B1
H
SYSCON XX10-
XXX0
B
– – EALE RMAP – – – XMAP
B8
H
2)
IP X000-
0000
B
– PSSC PT2 PS PT1 PX1 PT0 PX0
C0
H
2)
WDCON XXXX-
0000
B
– – – – OWDS WDTS WDT SWDT
1) “X” means that the value is undefined and the location is reserved.
2) Bit-addressable special function registers.
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
4) These are read-only registers.
5) The content of this SFR varies with the actual step of the C513A0: for example, 01
H
for the first step).
6) This register is only used for test purposes and must not be written during normal operation. Unpredictable
results may occur upon a write operation.