Infineon Technologies TC1796, Руководство пользователя, Страница: 1098 / 2150

TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-109 V2.0, 2007-07
Regs, V2.0
PSW Program Status Word F7E1 FE04
H
U, SV,
32 SV,
32 0000 0B80
H
PC Program Counter F7E1 FE08
H
U, SV,
32 SV,
32 DFFF FFFC
H
DE00 0000
H
– Reserved F7E1 FE0C
H
-
F7E1 FE10
H
nE nE –
SYSCON System Configuration
Register F7E1 FE14
H
U, SV,
32 SV,
32 0000 0000
H
CPU_ID CPU Identification
Register F7E1 FE18
H
U, SV,
32 U,
SV,
NC,
32 000A C0XX
H
– Reserved F7E1 FE1C
H
nE nE –
BIV Interrupt Vector Table
Pointer F7E1 FE20
H
U, SV,
32 SV,
E, 32 0000 0000
H
BTV Trap Vector Table Pointer F7E1 FE24
H
U, SV,
32 SV,
E, 32 A000 0100
H
ISP Interrupt Stack Pointer F7E1 FE28
H
U, SV,
32 SV,
E, 32 0000 0100
H
ICR ICU Interrupt Control
Register F7E1 FE2C
H
U, SV,
32 SV,
32 0000 0000
H
– Reserved F7E1 FE30
H
-
F7E1 FE34
H
nE nE –
FCX Free Context List Head
Pointer F7E1 FE38
H
U, SV,
32 SV,
32 0000 0000
H
LCX Free Context List Limit
Pointer F7E1 FE3C
H
U, SV,
32 SV,
32 0000 0000
H
– – F7E1 FE40
H
-
F7E1 FEFC
H
nE nE –
CPU Core General Purpose Register (GPRs)
2)
D0 Data Register 0 F7E1 FF00
H
– – XXXX XXXX
H
D1 Data Register 1 F7E1 FF04
H
– – XXXX XXXX
H
D2 Data Register 2 F7E1 FF08
H
– – XXXX XXXX
H
Table 18-33 Address Map of CPU Core SFRs & GPRs (cont’d)
Short
Name Description Address Access Mode Reset Value
Read
Write