Infineon Technologies TC1784, Руководство пользователя

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TC1784
Direct Memory Access Controller (DMA)
User´s Manual 11-23 V1.1, 2011-05
DMA, V3.03
Figure 11-14 Bus Switch
One access can be buffered in the bus interfaces.
Note: The accesses of the DMA Move Engine’s bus interfaces to the On Chip Bus
interfaces are always done in Supervisor Mode.
The arbiter/switch control unit arbitrates the requests from the connected active
interfaces (FPI Bus Interface, DMA Move Engines, MLI, Cerberus, ...) and grants the
buses connected to the switch for data transfers.
Table 11-1 and Table 11-2 are defining
the Bus Switch priorities for requests to the same On Chip Bus Interface. The arbitration
scheme is valid in case of a collision of requests from active peripherals connected to
the DMA Bus Switch (Move Engine, MLI, Cerberus) for the same resource (FPI Bus
Interface, LMB Bus Interface, DMA Peripheral Interface, Move Engine). The arbitration
is done for each Bus Switch request.
The general overview of the Bus Switch Priorities is given in
Table 11-1 . Additional
detailed information about the Move Engine priorities for concurrent on the Bus Switch
is described in
Table 11-2 .
In case of a collision of the DMA Move Engine requests on the DMA Bus switch for the
the same resource, a Move Engine Write has priority over a Move Engine Read. In case
of a collision of both Move Engines with concurrent read requests or concurrent write
requests for the same resource, the Move Engine number together with the
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