Infineon Technologies TC1784, Руководство пользователя

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TC1784
General Purpose I/O Ports and Peripheral I/O Lines (Ports)
User´s Manual 9-19 V1.1, 2011-05
Ports, V1.1
9.2.5 Emergency Stop Register
All GPIO lines have an emergency stop logic (see Figure 9-1 ).
Each GPIO line has its own emergency stop enable bit ENx that is located in the
emergency stop register Pn_ESR of Port n. If the emergency stop signal becomes
active, one of two states can be selected:
•
Emergency stop function disabled (ENx = 0):
A GPTA output line remains connected to the GPTA module (alternate function).
• Emergency stop function enabled (ENx = 1):
A GPTA output line is disconnected from the GPTA module (alternate function) and
connected to the corresponding bit of the Pn_OUT output register (the content of the
corresponding PCx bit fields in register Pn_IOCR is discarded)
Because very few GPIO lines do not have a GPTA outputs mapped to them, these GPIO
lines too have the emergency stop logic implemented, making in addition the
architecture uniform.
Pn_ESR (n=0-10)
Port n Emergency Stop Register (F000 0C50
H
+n*100
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN
15
EN
14
EN
13
EN
12
EN
11
EN
10
EN
9
EN
8
EN
7
EN
6
EN
5
EN
4
EN
3
EN
2
EN
1
EN
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Field Bits Type Description
ENx
(x = 0-15) x rw Emergency Stop Enable for Port n Pin x
This bit enables the emergency stop function for
GPIO lines used as GPTA outputs. If the emergency
stop condition is met and enabled, the output
selection is automatically switched from alternate
(GPTA output) function to GPIO output function.
0
B
Emergency stop function for Pn.x is disabled.
1
B
Emergency stop function for Pn.x is enabled.