Infineon Technologies TC1784, Руководство пользователя

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TC1784
On-Chip System Buses and Bus Bridges
User´s Manual 4-21 V1.1, 2011-05
Buses, V1.9
4.5 System Peripheral Bus
The TC1784 has one on-chip FPI Bus:
•
System Peripheral Bus (SPB)
– System bus for on-chip peripherals
This section gives an overview of the on-chip FPI Bus. It describes its bus control units,
the bus characteristics, bus arbitration, scheduling, prioritizing, error conditions, and
debugging support.
4.5.1 Overview
The FPI Bus interconnects the on-chip peripheral functional units with the TC1784
processor subsystem.
The FPI Bus is designed to be quick to be acquired by on-chip functional units, and quick
to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast
FPI Bus acquisition, which is required for time-critical applications.
The FPI Bus is designed to sustain high transfer rates. For example, a peak transfer rate
of up to 320 Mbyte/s can be achieved with the 32-bit data bus at 80 MHz bus clock.
Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate close to its
peak bandwidth.
Additional features of the FPI Bus include:
•
Optimized for high speed and high performance
• Support of multiple bus masters and pipelined transactions
• 32-bit wide address and data buses
• 8-, 16-, and 32-bit data transfers
• 64-, 128-, and 256-bit block transfers
• Central simple per-cycle arbitration
• Slave-controlled wait state insertion
• Support of atomic operations LDMST, ST.T and SWAP.W
The functional units of the TC1784 are connected to the FPI Bus via FPI Bus interfaces.
An FPI Bus interfaces acts as bus agents, requesting bus transactions on behalf of their
functional unit, or responding to bus transaction requests.
There are two types of bus agents:
•
FPI Bus master agents can initiate FPI Bus transactions and can also act as slaves.
• Slave agents can only react and respond to FPI Bus transaction requests in order to
read or write internal registers of slave modules as for example memories.
When an FPI Bus master attempts to initiate a transfer on the FPI Bus, it first signals a
request for bus ownership to the bus control unit (SBCU). When bus ownership is
granted by the SBCU, an FPI Bus read or write transaction is initiated. The unit targeted
by the transaction becomes the FPI Bus slave, and responds with the requested action.