Infineon Technologies TC1784, Руководство пользователя

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TC1784
System Control Unit (SCU)
User´s Manual 3-50 V1.1, 2011-05
32-bit SCU, V1.18
3.1.2.1 Clock Control Register CLC
All CLC registers have basically the same bit and bit field layout. However, not all CLC
register functions are implemented for each peripheral module.
Table 3-1 defines in
detail which bits and bit fields of the CLC registers are implemented for each clock
control register.
The CLC register controls the generation of the peripheral module clock which is derived
from the system clock. The following functions for the module are associated with the
CLC register:
•
Peripheral clock static on/off control
• Module clock behavior in Sleep Mode
• Operation during Suspend Mode
• Fast Shut-off Mode control
Module Enable/Disable Control
If a module is not used at all by an application, it can be completely shut off by setting bit
DISR in its CLC register. For peripheral modules with a run mode clock divider field
RMC, a second option to completely switch off the module is to set bit field RMC to 00
H
.
This also disables the module’s operation.
The status bit DISS always indicates whether a module is currently switched off
(DISS = 1) or switched on (DISS = 0).
Write operations to the non CLC registers of disabled modules are not allowed.
However, the CLC of a disabled module can be written. An attempt to write to any of the
other writable registers of a disabled module except CLC will cause the corresponding
Bus Control Unit (BCU) to generate a bus error.
A read operation of registers of a disabled module is allowed and does not generate a
bus error.
When a disabled module is switched on by writing an appropriate value to its MOD_CLC
register (DISR = 0 and RMC (if implemented) > 0), status bit DISS changes from 1 to 0.
During the phase in which the module becomes active, any write access to
corresponding module registers (when DISS is still set) will generate a bus error.
Therefore, when enabling a disabled module, application software should check after
activation of the module once (read back of the CLC register) to find out whether DISS
is already cleared, before a module register (including the CLC register) will be written to.
Sleep Mode Control
The EDIS bit in the CLC register controls whether or not a module is stopped during
Sleep Mode. If EDIS is 0, a Sleep Mode request can be recognized by the module and,
when received, its clock is shut off.