Infineon Technologies TC1784, Руководство пользователя

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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual 21-10 V1.1, 2011-05
GPTA
®
v5, V1.14
21.3.2 Clock Generation Cells
As described in detail in the following sections, the Clock Generation Cells (CGC)
provides the following signal pre-processing cells:
•
Filter and Prescaler Cell (FPC)
• Phase Discrimination Logic (PDL)
• Duty Cycle Measurement cell (DCM)
• Digital Phase Locked Loop Cell (PLL)
• Clock Distribution Cells (CDC)
The Filter and Prescaler Cells (FPC) provide input noise filtering using a debounce
filter. FPCs are also able to operate as a prescaler for the GPTA
®
v5 module clock and
external signals. Each FPC can select among different data and clock input signals.
The
Phase Discrimination Logic (PDL) is able to decode FPC debounce filtered and
phase encoded signals coming from a position and rotation direction sensor system. In
the PDL, phase encoding can be bypassed.
The
Duty Cycle Measurement Cells (DCM) provide signal measurement capabilities
(timer plus capture register, single and double capture on rising and falling edges or
both) as well as missing pulse detection/reconstruction functions.
The
Digital Phase Locked Loop (PLL) is intended to generate a higher resolution clock
out of the values measured by DCM cells. Any arbitrary multiplication factor between 1
and 65535 is supported and may be changed from input clock period to input clock
period.
The
Clock Distribution Cells (CDC) provide all Local and Global Timer Cells with a
variety of different clock signals. It is equipped with GPTA
®
v5 module clock prescalers
and multiplexers supporting alternate clock sources.
Figure 21-3 shows how the cells of the CGC are interconnected. The external interface
signals of the CGC are:
•
GPTA
®
v5 module clock
f
GPTA
• GPTA
®
v5 module input signals (connected to the FPCs)
• Clock bus outputs (generated by the CDC)
• PDL bus outputs
• External PLL clock inputs (fed into CDC)