Infineon Technologies TC1784, Руководство пользователя

Страница: 165 / 2350

TC1784
CPU Subsystem
User´s Manual 2-75 V1.1, 2011-05
CPU, V3.03
Instruction Cache Bypass
The Instruction Cache may be bypassed, under control of PMI_CON0.PCBYP, to
provide a direct instruction fetch path for the CPU Fetch Unit. The default value of
PMI_CON0.PCBYP is such that the ICACHE is bypassed after reset. ICACHE bypass
should be disabled during initialization to enable the ICACHE.
Whilst ICACHE bypass is enabled, a fetch request by the CPU to a cacheable address
will result in a forced cache miss, such that the cache controller issues a standard refill
sequence and supplies instruction half-words to the CPU using instruction streaming,
without updating the cache contents. Any valid cache lines within the ICACHE will
remain valid and unchanged whilst the ICACHE is bypassed. As such, instruction fetch
requests to cacheable addresses with ICACHE bypass enabled behave identically to
instruction fetch requests to non-cacheable addresses.
Instruction Cache Invalidation
The PMI does not have automatic cache coherency support. Changes to the contents of
memory areas external to the PMI that may have already been cached in the ICACHE
are not detected. Software must provide the cache coherency in such a case. The PMI
supports this via the cache invalidation function. The ICACHE contents may be globally
invalidated by writing a ‘1’ to PMI_CON1.PCINV. The ICACHE invalidation is performed
over multiple cycles by a hardware state machine which cycles through the ICACHE
entries marking each as invalid. The status of the ICACHE invalidation sequence may
be determined by reading the PMI_CON1.PCINV bit.
2.14.5 Program Line Buffer
The PMI module contains a 256-bit Program Line Buffer (PLB). For accesses to
cacheable addresses the PLB acts as a streaming buffer for the main instruction cache.
Instruction cache refill sequences transfer data to the PLB and the immediately to the
TriCore CPU without updating the main instruction cache. The PLB contents are then
transferred to the main instruction cache on the next instruction cache miss.
Program fetch requests to non-cacheable addresses utilize the PLB as a single line
cache. A single valid bit is associated with the PLB, denoting that the PLB contents are
valid. As such all fetch requests resulting in an update of the PLB, whether to a
cacheable address or not, are implemented as LMB Burst Transfer 4 (BTR4)
transactions, with the critical double-word of the PLB line being fetched first size.