13. I2C Registers > Register Descriptions
420
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
13.2.3
I
2
C Master Configuration Register
This register contains options that apply to master operations initiated through the
. The configuration specifies the properties of the external slave device to which a read or
write transaction will be directed.
Register name: I2C_MST_CFG
Reset value: Undefined
Register offset: 0x1D108
Bits
0
1
2
3
4
5
6
7
00:07
Reserved
08:15
DORDER
Reserved
PA_SIZE
16:23
Reserved
24:31
Reserved
DEV_ADDR
Bits
Name
Description
Type
Reset
Value
00:07
Reserved
Reserved
R
0x00
08
DORDER
Data Order
0 = Data from/to data registers is ordered (processed) from
MSB to LSB within an I
2
C transaction.
1 = Data from/to data registers is ordered (processed) from
LSB to MSB within an I
2
C transaction.
Data registers are
C Master Transmit Data Register”
C Master Receive Data Register”
R/W
0
09:13
Reserved
Reserved
R
0x00
14:15
PA_SIZE
Peripheral Address Size
00 = No peripheral address used
01 = 8-bit peripheral device addressing using LSB of
PADDR
10 = 16-bit peripheral device addressing using MSB and
LSB of PADDR (in that order)
11 = Reserved (handled as 00)
This field selects the number of bytes in the peripheral
address for master transactions. The peripheral address
itself is specified in the
.
R/W
Undefined
16:24
Reserved
Reserved
R
0x000
25:31
DEV_ADDR
Device Address
Specifies the 7-bit device address to select the I
2
C device
for a read or write transaction initiated through the
.
R/W
Undefined
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Страница 504: ...B Clocking P_CLK Programming 504 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...
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