4. Addressing
47
Tsi384 User Manual
May 5, 2014
Integrated Device Technology
www.idt.com
The memory-mapped I/O address range that is defined by the Base and Limit registers are always
aligned to a 1-MB boundary and has a size granularity of 1 MB.
4.3
Prefetchable Space
The prefetchable address space maps memory address ranges of devices that are prefetchable; that is,
devices that do not have side-effects during reads. For PCI-to-PCIe reads, prefetching occurs in this
space for all memory read commands (MemRd, MemRdLine, MemRdMult) issued on the PCI bus. For
these Read commands, the Tsi384 prefetches data according to prefetching algorithm defined in
. For PCIe-to-PCI/X reads, the number of bytes to be read is determined by the
Memory Read Request.
The Prefetchable Memory Base, Prefetchable Memory Limit, Prefetchable Base Upper 32 Bits, and
Prefetchable Limit Upper 32 Bits registers in the bridge configuration header specify an address range
that is used by the bridge to determine whether to forward PCIe and PCI/X memory read and memory
write transactions across the bridge. The prefetchable memory address range defined by these registers
is always aligned to a 1-MB boundary and has a size granularity of 1 MB. If the address specified by
the Prefetchable Memory Base and Prefetchable Base Upper 32 Bits registers is set to a value higher
than the address specified by the Prefetchable Memory Limit and Prefetchable Limit Upper 32 Bits
registers, the address range is disabled.
Following register bits effect the response by the bridge to memory transactions:
•
Memory Enable bit in
“PCI Control and Status Register”
•
Bus Master Enable bit in
“PCI Control and Status Register”
•
VGA Enable bit in
“PCI Bridge Control and Interrupt Register”
The Tsi384 forwards memory transactions downstream from its PCIe Interface to its PCI/X Interface if
a memory address is in the range defined by the Prefetchable Memory Base and Prefetchable Memory
Limit registers. Conversely, a memory transaction on the PCI/X Interface that is within this address
range is not be forwarded upstream to the PCIe Interface. Any memory transactions on the PCI/X
Interface that are outside this address range are forwarded upstream to the PCIe Interface (provided
they are not in the address range defined by the memory-mapped I/O address range registers).
If the Prefetchable Memory Base is programmed to have a value greater than the Prefetchable Memory
Limit, then the prefetchable memory range is disabled. In this case, all memory transaction forwarding
is determined by the memory-mapped I/O base and limit registers. Note that all four prefetchable base
and limit registers must be considered when disabling the prefetchable range.
Unlike non-prefetchable memory-mapped I/O memory, Prefetchable memory can be located below,
above, or span across the first 4-GB address boundary.
illustrates a prefetchable memory
window that spans across the 4-GB address boundary. Memory locations above 4 GB are accessed
using 64-bit addressing. PCIe memory transactions that use the Short Address (32-bit) format can
target a non-prefetchable memory window or the portion of a prefetchable memory window that is
below the first 4-GB address boundary. Memory transactions that use the Long Address (64-bit) format
can target the portion of a prefetchable memory window that is at or above the first 4-GB address
boundary.
Содержание TSI384
Страница 1: ... IDT Tsi384 PCIe to PCI Bridge User Manual May 5 2014 ...
Страница 10: ...Contents 10 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...
Страница 36: ...2 Signal Descriptions 36 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...
Страница 56: ...4 Addressing 56 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...
Страница 62: ...5 Configuration Transactions 62 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...
Страница 74: ...6 Bridging 74 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...
Страница 78: ...7 PCI X Arbitration 78 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...
Страница 128: ...11 Power Management 128 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...
Страница 136: ...12 Serial EEPROM 136 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...
Страница 142: ...13 JTAG 142 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...
Страница 268: ...16 Packaging 268 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...
Страница 276: ...276 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...
Страница 280: ...Index 280 Tsi384 User Manual May 5 2014 Integrated Device Technology www idt com ...