3. RapidIO Lanes > Lane, PLL, and Port Power-Down
CPS-1848 User Manual
75
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
3.3
Lane, PLL, and Port Power-Down
Systems operate more efficiently if they can save the power consumed by unused lanes, PLLs, and ports. The CPS-1848
allows software to manually or automatically turn off these resources when not required, as described below:
• Lane power-down – To disable an unused lane, set LANE_DIS to 1 in the
.
• PLL power-down – If all lanes associated with a PLL are disabled, additional power savings can be realized by powering
down the PLL. To power down a PLL, set the PLL_PWR_DWN bit to 1 in the
PLL {0..11} Control 1 Register
• Port power-down – If a port does not have any lanes connected to it, the port is automatically powered down.
3.4
Port and Lane Initialization Sequence
The CPS-1848’s S-RIO ports support a RapidIO standard, multi-step initialization process. For more information, see Part 6 of
the RapidIO Specification (Rev. 2.1). Port and lane initialization follows these steps:
1. Achieve lane synchronization. When lane synchronization is achieved, valid 10-bit code groups are received reliably.
— The number of valid code groups that must be received error-free before deciding that lane synchronization has been
achieved is controlled through VMIN in the
Port {0..17} Lane Synchronization Register
2. IDLE sequence negotiation. The CPS-1848 attempts to use the RapidIO Gen2 IDLE2 sequence for all lane speeds. If the
CPS-1848 detects that the link partner is using the RapidIO Gen1 IDLE1 sequence, it selects the IDLE1 sequence.
— The IDLE sequence selected is located in the IDLE_SEQ bit of the
Port {0..17} Error and Status CSR
.
3. If the IDLE2 sequence is active, the CPS-1848 performs the following:
— Lane polarity inversion detection and correction. To simplify board layouts, the CPS-1848 can automatically detect and
correct when the positive and negative traces of a differential pair for a lane are inverted. Lane inversion status for each
lane is located in the
.RX_INVERT bit.
— Lane reversal detection and correction: the CPS-1848 can automatically detect and correct if the lanes on a multilane
port are connected in reverse order. This can simplify board layouts. Lane reversal status for each CPS-1848 port is
located in
Port {0..17} Implementation Specific Error Detect Register
.REORDER.
4. Whether IDLE1 or IDLE2 is selected, multilane ports attempt to align the different lanes to ensure that striped data is correctly
decoded. When IDLE2 is active, this step occurs once lane polarity and lane reversal have been resolved. Lane alignment
occurs simultaneously with transmitter emphasis/receiver equalization optimization. Note that this step is not necessary for
ports constrained to operate as single lane (1x) ports.
5. The widest supported port operating width will be selected once all steps have completed. The maximum time allowed for
IDLE sequence negotiation, IDLE2 sequence optimization, and lane alignment (if necessary) is 32 milliseconds. The
operating width of the port is located in the
.INIT_PWIDTH field.
6. Status control symbols are transmitted and received to ensure that control symbols can be exchanged correctly on the port.
It is not possible to disable the use of the IDLE2 sequence for 6.25 Gbaud lane rates. For lane rates of
less than 6.25 Gbaud, IDLE2 sequence can be disabled by clearing IDLE2_EN in the
The IDLE2 sequence must be used for 6.25 Gbaud lane rates.
RapidIO Gen1 devices support the IDLE1 sequence only. It is not possible to reverse the lane ordering
of a port when the IDLE1 sequence is used; therefore, the link partner’s lanes must be connected in the
correct order.
The use of lane reversal is not recommended for links that support hot swap, or that are expected to
successfully downgrade if there is a hardware error.
