FT1A S
MART
A
XIS
U
SER
’
S
M
ANUAL
FT9Y-B1382
5-23
5: B
ASIC
I
NSTRUCTIONS
SFR and SFRN (Forward and Reverse Shift Register)
SmartAxis CPU modules have a shift register consisting of 128 bits which are allocated to R0 through R127. Any number of
available bits can be selected to form a train of bits which store on or off status. The on/off data of constituent bits is shifted in the
forward direction (forward shift register) or in the reverse direction (reverse shift register) when a pulse input is turned on.
Forward Shift Register (SFR)
When SFR instructions are programmed, two addresses are always required. The SFR instruction is entered, followed by a shift
register number selected from appropriate device addresses. The shift register number corresponds to the first, or head bit. The
number of bits is the second required address after the SFR instruction.
The SFR instruction requires three inputs. The forward shift register circuit must be programmed in the following order: reset
input, pulse input, data input, and the SFR instruction, followed by the first bit and the number of bits.
Reset Input
The reset input will cause the value of each bit of the shift register to return to zero. Initialize pulse special internal relay, M8120,
may be used to initialize the shift register at start-up.
Pulse Input
The pulse input triggers the data to shift. The shift is in the forward direction for a forward shift register and in reverse for a
reverse shift register. A data shift will occur upon the leading edge of a pulse; that is, when the pulse
turns on
. If the pulse has
been on and stays on, no data shift will occur.
Data Input
The data input is the information which is shifted into the first bit when a forward data shift occurs, or into the last bit when a
reverse data shift occurs.
Note:
When power is turned off, the statuses of all shift register bits are normally cleared. It is also possible to maintain the statuses of shift
register bits by using the Function Area Settings as required. See page 5-5.
Ladder Diagram
Structural Diagram
I2
I0
R0
Reset
Data
I1
Pulse
R1 R2 R3
Shift Direction
First Bit: R0
# of Bits: 4
I0
I1
SFR
R0
4
I2
Reset
Pulse
Data
First Bit
# of Bits
Structural Diagram
I2
I0
R0
Reset
Data
I1
Pulse
R1 R2 R3
Shift Direction
# of Bits: 4
LOD
LOD
LOD
SFR
I0
I1
I2
R0
4
Program List
Instruction
Data
First Bit
# of Bits
R0 to R127
1 to 128
For restrictions on ladder programming of shift register instructions, see page 5-32.
Caution
Содержание microsmart pentra
Страница 1: ...FT1A SERIES FC9Y B1382 Ladder Programming Manual ...
Страница 6: ...Preface 5 FT1A SMARTAXIS USER S MANUAL FT9Y B1382 ...
Страница 104: ...7 DATA COMPARISON INSTRUCTIONS 7 10 FT1A SMARTAXIS USER S MANUAL FT9Y B1382 ...
Страница 122: ...8 BINARY ARITHMETIC INSTRUCTIONS 8 18 FT1A SMARTAXIS USER S MANUAL FT9Y B1382 ...
Страница 138: ...10 SHIFT ROTATE INSTRUCTIONS 10 12 FT1A SMARTAXIS USER S MANUAL FT9Y B1382 ...
Страница 162: ...11 DATA CONVERSION INSTRUCTIONS 11 24 FT1A SMARTAXIS USER S MANUAL FT9Y B1382 ...
Страница 188: ...12 CALENDAR COMPARISON INSTRUCTIONS 12 26 FT1A SMARTAXIS USER S MANUAL FT9Y B1382 ...
Страница 198: ...15 REFRESH INSTRUCTIONS 15 4 FT1A SMARTAXIS USER S MANUAL FT9Y B1382 ...
Страница 202: ...16 INTERRUPT CONTROL INSTRUCTIONS 16 4 FT1A SMARTAXIS USER S MANUAL FT9Y B1382 ...
Страница 266: ...20 DUAL TEACHING TIMER INSTRUCTIONS 20 4 FC5A MICROSMART USER S MANUAL FC9Y B1273 ...
Страница 318: ...25 USER COMMUNICATION INSTRUCTIONS 25 22 FT1A SMARTAXIS USER S MANUAL FT9Y B1382 ...