ICS Advent ADIO1600 Series, Руководство по эксплуатации продукта, Страница: 51 / 72

Chapter 7: Programmable interval Timer
Manual Number: 00650-004-5 Page 7-3
SC0-SC1: These bits select the counter that the control byte is destined for.
SC1 SC0 Function
0 0 Program Counter #0
0 1 Program Counter #1
1 0 Program Counter #2
1 1 Read/Write Cmd.*
* See section on READING AND LOADING THE COUNTERS.
RW0-RW1: These bits select the read/write mode of the selected counter.
RW1 RW0 Counter Read/Write Function
0 0 Counter Latch Command
0 1 Read/Write LS Byte
1 0 Read/Write MS Byte
1 1 Read/Write LS Byte, then MS Byte
M0-M2: These bits set the operational mode of the selected counter.
MODE M2 M1 M0
0 0 0 0
1 0 0 1
2 X 1 0
3 X 1 1
4 1 0 0
5 1 0 1
BCD: Set the selected counter to count in binary (BCD = 0) or BCD (BCD = 1).
Reading and Loading the Counters
If you attempt to read the counters on the fly when there is a high input frequency, you will most
likely get erroneous data. This is partly caused by carries rippling through the counter during the
read operation. Also, the low and high bytes are read sequentially rather than simultaneously and,
thus, it is possible that carries will be propagated from the low to the high byte during the read cycle.
To circumvent these problems, you can perform a counter-latch operation in advance of the read
cycle. To do this, load the RW1 and RW2 bits with zeroes. This instantly latches the count of the
selected counter(selected via the SC1 and SC0 bits) in a 16-bit hold register. (An alternative method
of latching counter(s) which has an additional advantage of operating simultaneously on several
counters is by use of a readback command to be discussed later.) A subsequent read operation on
the selected counter returns the held value. Latching is the best way to read a counter on the fly
without disturbing the counting process. You can only rely on directly read counter data if the
counting process is suspended while reading, by bringing the gate low, or by halting the input
pulses.