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PCI-82x Series Cards
Multifunction Boards
User Manual, Ver. 1.5, Jan. 2017, PMH-024-15, Page: 54
6.5.7
Read the Status of the FIFO/JP1/ADC
(Read)wBase+0x10
Read the Status of the FIFO/JP1/ADC
Bit
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Data
FF
FH
Fe
A0
D0
x
x
x
x
x
x
x
x
x
x
x
This register is used to read the current status of the FIFO, the JP1 Jumper and the A/D Conversion.
Refer to the following table for details:
Data
Read Value
0
1
D0
JP1 is set to Differential mode
JP1 is set to Single-ended mode
A0
The ADC is Ready
The ADC is Busy
FF
The FIFO is Full
The FIFO isn’t Full
FH
The FIFO is Half Full
The FIFO isn’t Half Full
FE
The FIFO is Empty
The FIFO isn’t Empty
6.5.8
Read/Write the Base Frequency and the MagicScan
Control Settings
(Read/Write)wBase+0x14 Read/Write the Base Frequency and the MagicScan Control
Settings
Bit
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Data
E0
x
x
x
CK3 CK2 CK1 CK0
S4
S3
S2
S1
S0
M2
M1
M0
This register is used to set/read the trigger edge settings, the base frequency, the MagicScan mode
and the total number of channels to be scanned.
Note that Bits C to E are reserved.