IBM z13s, Техническое руководство

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IBM z13s Technical Guide
9.3 RAS functions
Unscheduled, scheduled, and planned outages have been addressed for the mainframe
family of servers for many years:
Unscheduled This outage occurs because of an unrecoverable malfunction in a hardware
component of the server.
Scheduled This outage is caused by changes or updates that must be done to the
server in a timely fashion. A scheduled outage can be caused by a
disruptive patch that must be installed, or other changes that must be made
to the system.
Planned This outage is caused by changes or updates that must be done to the
server. A planned outage can be caused by a capacity upgrade or a driver
upgrade. A planned outage is usually requested by the customer, and often
requires pre-planning. The z13s design phase focused on this pre-planning
effort, and was able to simplify or eliminate it.
A fixed-size hardware system area (HSA) of 40 GB helps eliminate pre-planning
requirements for HSA, and helps provide flexibility to dynamically update the configuration.
It is possible to perform the following tasks dynamically:
򐂰 Add a logical partition (LPAR) (up to 40)
򐂰 Add a logical channel subsystem (LCSS) (up to 3)
򐂰 Add a subchannel set (up to 3)
򐂰 Add a logical CP to an LPAR
򐂰 Add a cryptographic coprocessor
򐂰 Remove a cryptographic coprocessor
򐂰 Enable I/O connections
򐂰 Swap processor types
򐂰 Add memory by using LICCC
򐂰 Add a physical processor
In addition, by addressing the elimination of planned outages, the following tasks are also
possible:
򐂰 Concurrent driver upgrades
򐂰 Periodic concurrent microcode control level (MCL) installation
򐂰 Concurrent and flexible Customer Initiated Upgrades (CIUs)
For a description of the flexible CIUs, see Chapter 8, “System upgrades” on page 311.
9.3.1 Unscheduled outages
An unscheduled outage occurs because of an unrecoverable malfunction in a hardware
component of the z13s server.
The following improvements are designed to minimize unscheduled outages:
򐂰 Continued focus on firmware quality
For LIC and hardware design, failures are eliminated through rigorous design rules,
design walk-throughs, and peer reviews. Failures are also eliminated through element,
subsystem, and system simulation, and extensive engineering and manufacturing testing.