IBM S822LC, Технический обзор и введение

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Chapter 1. Architecture and technical description
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1.7 The POWER8 processor
This section introduces the latest processor in the Power Systems product family and
describes its main characteristics and features in general.
The POWER8 processor in the S822LC for High Performance Computing is unique to the
8335-GTB. Engineers removed the A-Bus interface along with SMP over PCI support to make
room for the NVLink interface. The resulting chip grows slightly from 649 mm
2
to 659 mm
2
.
1.7.1 POWER8 processor overview
The POWER8 processor is manufactured by using the IBM 22 nm Silicon-On-Insulator (SOI)
technology. Each chip is 649 mm
2
and contains 4.2 billion transistors. As shown in Figure 1-5,
the chip contains up to 12 cores, two memory controllers, Peripheral Component Interconnect
Express (PCIe) Gen3 I/O controllers, and an interconnection system that connects all
components within the chip. Each core has 512 KB of L2 cache, and all cores share 96 MB of
L3 embedded DRAM (eDRAM). The interconnect also extends through module and system
board technology to other POWER8 processors in addition to DDR4 memory and various I/O
devices.
POWER8 processor-based systems use memory buffer chips to interface between the
POWER8 processor and DDR4 memory. Each buffer chip also includes an L4 cache to
reduce the latency of local memory accesses.
Figure 1-5 The POWER8 processor chip