IBM IntelliStation POWER 285, Технический обзор и введение

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Chapter 2. Architecture and technical overview
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򐂰 The TLB size doubled in the over the POWER5 processors
The TLB in has 2048 entries.
򐂰
Floating-point round to integer instructions
New instructions (frfin, frfiz, frfip, frfim) have been added to round floating-point numbers
integers with the following rounding modes: nearest, zero, integer plus, integer minus.
򐂰 Improved floating-point performance
򐂰 Lock performance enhancement
򐂰 Enhanced SLB read
򐂰 True Little-Endian mode
This is support for the True Little-Endian mode as defined in the PowerPC architecture.
򐂰 Double the SMP support
Changes have been made in the fabric, L2 and L3 controller, memory controller, GX
controller and processor RAS to provide support for the QCM that allows the SMP system
sizes to be double that is available in POWER5 DCM-based servers. Current
implementations only supports single address loop.
򐂰 Several enhancements in the memory controller for improved performance
The controller comes ready to support for DDR-2 667 MHz DIMMs in the future.
򐂰 Enhanced redundancy in L1 cache, L2 cache and L3 directory
Independent control of the L2 cache and the L3 directory for redundancy to allow
split-repair action has been added. More word line redundancy has been added in the L1
Dcache. In addition, Array Built-In Self Test (ABIST) column repair for the L2 cache and
the L3 directory has been added.
2.2 Processor and cache
In the IntelliStation POWER 285 system, the processor has been packaged with
the L3 cache chip into a cost-effective, dual-core module (DCM) package. The storage
structure for the processor is a distributed memory architecture that provides high
memory bandwidth. The DCM and its optional L3 cache are directly soldered to the system
board. They are interfaced to eight memory slots, controlled by two Synchronous Memory
Interface (SMI-II) controllers that are in close physical proximity to the DCM. The IntelliStation
POWER 285 system supports one microprocessor with either one or two active
cores sharing the integrated 36 L3 cache. See Figure 2-3 on page 12 for a
processor core layout view.