IBM CPC700, Руководство пользователя

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CPC700 User’s Manual—Preliminary 7-11
7.3 FIFO Operation
7.3.1 Interrupt Mode
7.3.1.1 Receiver
Receiver interrupts occur as described below when the receiver FIFO and receiver interrupts are enabled
by setting FIFO control register (FCR) bit 7 and interrupt enable register (IER) bit 7 to logic 1.
The received data available interrupt is issued when the number of characters in the FIFO has reached the
trigger level programmed into the FCR. This interrupt will be reset to logic 0 when the FIFO character count
drops below this trigger level.
The IIR received data available indicator will be issued when the number of characters in the FIFO has
reached the trigger level programmed into the FCR. This indicator will be reset to logic 0 when the FIFO
character count drops below this trigger level.
The receiver line status interrupt (IIR = 0xC6) is a top priority interrupt, whereas the received data available
interrupt (IIR = 0xC4) is a second priority interrupt.
The data ready bit (bit 7 of LSR) is set as soon as a character is transferred from the shift register to the
receiver FIFO. This bit is reset when the FIFO is empty.
Receiver timeout interrupts will occur as described below when the receiver FIFO and receiver interrupts
are enabled by setting FCR bit 7 and IER bit 7 to logic 1.
A FIFO timeout will occur when:
At least one character is in the receiver FIFO, no serial characters have been received for four serial
character time periods, and the processor has not read the FIFO for four serial character time periods. A
serial character time period is
1/(baud rate) * (# start bits + word # parity bits + # stop bits)
For example, the serial character time period for an 8-bit word with one parity bit, two stop bits at 56K
baud is
1/(56000) * (1 + 8 + 1 + 2) = 214.3
µ
s
so the timeout would occur after 857.1
µ
s, if the above conditions hold.
When a timeout interrupt has occurred, it is cleared and its timer reset when the processor reads one
character from the receiver FIFO.
When a timeout interrupt has NOT occurred, its timer is reset after a new serial character is received or the
processor reads the receiver FIFO.
7.3.1.2 Transmitter
Transmitter interrupts occur, as described below, when the transmitter FIFO and transmitter interrupts are
enabled by setting FCR bit 7 and IER bit 6 to logic 1.
The transmitter holding register interrupt (IIR = 0xC2) occurs when the transmitter holding register is
empty, and is cleared as soon as the transmitter holding register is written to or the IIR is read. One to 16
characters may be written to the transmitter FIFO while servicing this interrupt.
The transmitter FIFO empty indications are delayed by one character time minus the last stop bit time
whenever the following event occurs: THRE = 1 and there were less than two bytes simultaneously present