IBASE Technology MI945X, Руководство пользователя

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BIOS SETUP
MI945X User’s Manual 33
Advanced Chipset Features
This Setup menu controls the configuration of the chipset.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
System BIOS Cacheable Enabled ITEM HELP
Memory Hole at 15M-16M Disabled
Support FSB and DDR3 667Mhz Disabled
PCI Express Root Port Func Press Enter
VT-d Disable
** VGA Setting **
PEG/Onchip VGA Control Auto
PEG Force X1 Disabled
On-Chip Frame Buffer Size 64MB
DVMT Mode Enable
Total GFX Memory 128MB
PAVP Mode PAVP-Lite
** VGA Boot Device Setting **
Boot Display CRT + LVDS
SDVO Device Setting None
SDVO LVDS Protocol 1 Ch SPGW,24bit
SDVO Panel Number 1024x768
Active LVDS Device No LVDS
Integrated LVDS Protocol 18bit
Panel Scaling AUTO
Panel Type 1024x768 SC/DC
System BIOS Cacheable
The setting of Enabled allows caching of the system BIOS ROM at
F000h-FFFFFh, resulting in better system performance. However, if
any program writes to this memory area, a system error may result.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be
reserved for ISA cards. This memory must be mapped into the memory
space below 16 MB. The choices are
Enabled and Disabled .
Support FSB and DDR3 667Mhz
The options are Enabled and Disabled .
VT-d
The options are Enabled and Disabled .