BIOS SETUP
38
IB730 User’s Manual
Chipset Features Setup
This Setup menu controls the configuration of the chipset.
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
SDRAM RAS-to-CAS Delay
: 3
CPU Warning Temperature
: Disabled
SDRAM RAS Precharge Time
:
3
Current System Temp.
: 41
°
C/ 105
°
F
SDRAM CAS Latency Time
3
Current CPU Temp.
: 27
°
C/ 80
°
F
SDRAM Precharge Control
:
Disabled
Current System Temp.
: 34
°
C/ 93
°
F
DRAM Integrity Mode:
:
Non-ECC
Current CPU Fan Speed
: 2789 RPM
System BIOS Cacheable
:
Disabled
Current Chassis Fan Speed
: 2045 RPM
Video BIOS Cacheable
:
Disabled
Video RAM Cacheable
:
Disabled
8 Bit I/O Recovery Time
:
3
16 Bit I/O Recovery Time
:
2
VCCP (V) :
1.98 V
VTT (V) :
1.50 V
Memory Hole At 15MB-16MB
:
Disabled
VCC3 (V) :
3.45 V
+ 5 V
:
4.99 V
Passive Release
:
Enabled
+12 V
: 12.46 V
-12 V
:
-12.54V
Delayed Transaction
:
Disabled
-5V
: - 5.21 V
AGP Aperture Size (MB)
:
64
ESC : Quit
á
â
à
ß
: Select Item
Auto Detect DIMM/PCI Clock
:
Disabled
F1 : Help
PU/PD/+/- : Modify
Spread Spectrum
:
Disabled
F5 : Old Values
(Shift) F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
SDRAM RAS-to-CAS Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This field allows you to determine the timing of transition
from Row Address Strove (RAS) to Column Address Strobe (CAS). The
default setting is
3
.
SDRAM RAS Precharge Time
The precharge time is the number of cycles it takes for the RAS to
accumulate its charge before DRAM refresh. If insufficient time is
allowed, refresh may be incomplete and the DRAM may fail to retain
data. The default setting is
3
.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer. The default value is
3
.
SDRAM Precharge Control
By default, DRAM Integrity Mode is set to Non-ECC.
DRAM Integrity Mode
By default, the SDRAM Precharge Control field is set to
Disabled
.