HP Integrity rx1620, Руководство по эксплуатации

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System Information
System Board
Appendix B
127
Chip Spare Functionality
The memory subsystem design supports chip spare functionality. Chip spare enables an entire SDRAM chip
on a DIMM to be bypassed (logically replaced) in the event that a multi-bit error is detected on that SDRAM.
In order to use the chip spare functionality, only DIMMs built with x4 SDRAM parts can be used, and these
DIMMs must be loaded in quads (2 DIMMs per memory cell, loaded in the same location in each memory cell).
Each DIMM within a quad must be identical to all the other DIMMs in the quad.
Using the DIMM loading order indicated in the Memory Block Diagram, chip spare can be achieved if 4
identical DIMMs are loaded in the slots DIMM0A/B and DIMM1A/B. Addition of a pair of DIMMs beyond this
quad (DIMM2A/B) negates the ability to support chip spare, so the maximum DIMM count with chip spare
enabled is four. Note that if the system configuration is ever expanded to accommodate 8 DIMMs, chip spare
is enabled if identical DIMM quads are loaded in slots DIMM0/1(A/B) and DIMM2/3(A/B).
Chip spare enables an entire DDR SDRAM chip on a DIMM to be bypassed in the event that a multi-bit error
is detected on the DDR SDRAM. In order to use the chip spare functionality on your system, only DIMMs
built with
×
4 DDR SDRAM parts can be used, and these DIMMs must be loaded in quads.
Serial Presence Detect (SPD)
Each DIMM contains an inter IC (I2C) EEPROM whose content describes the module's characteristics: speed,
techno, revision, vendor, and so on. This feature is called serial presence detect (SPD). Firmware typically
uses this information to detect unmatched pairs of DIMMs, and configure certain memory subsystem
parameters. The SPD information for DIMMs loaded in the system will also be accessible to the baseboard
management controller (BMC) through the I2C bus.
I/O Bus Interface
The I/O bus interface provides these features:
• Provides industry standard PCI-X 66MHz, 64 data bit support.
• Uses 3.3V PCI only.
• Optimizes for DMA performance.
• Supports 3.3V or Universal keyed PCI cards.
• Supports up to two PCI sockets.
Processor Dependent Hardware Controller
The processor dependent hardware controller (PDH) provides these features:
• 16-bit PDH bus with reserved address space for:
• Flash memory
4GB /
16GB 2048MB
DIMM DIMM36 x 128Mb x 4 DDR SDRAMs (512Mb, stacked)
Table B-1 Memory Array Capacities (Continued)
Min. /
Max
Memory
Size
Single
DIMM
Size
DDR SDRAM Count, Type and Technology