HT98R068 Two-way Radio MCU
PLL Control Flow - for MCU
Flow description:
<Set … PLL>: Setup the PLL divider and PLL enable.
<Delay10ms>: Delay 10ms which is to wait for the PLL to stabilise
<CLKMOD=0>: Set the MCU to be in the PLL mode.
Controlling the Audio Processor
Audio Processor Reset
After the PLL is setup, the next step is to enable the audio processor by setting the
CTRL2[4] bit, which is the audio processor reset signal control bit. Use a 1
0
1
sequence, which drives POR=0. Also do not set CTRL2[4]=1 when configuring the PLL.
After a reset, it is necessary to wait for 100ms~300ms (Fsys_Audo=16MHz *note) before
sending instructions. This waiting period is for the audio processor internal initialisation,
including RAM initialization, ADC, DAC...etc. Any SPI commands during this period will
be invalid as shown below:
5
