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Configuring the Event Counter Mode
In this mode, a number of externally changing logic events, occurring on external pin PC1/TMR,
can be recorded by the internal timer. For the timer to operate in the event counting mode, bits
TM1 and TM0 of the TMRC register must be set to 0 and 1 respectively. The timer-on bit, TON
must be set high to enable the timer to count. With TE low, the counter will increment each time the
PC1/TMR pin receives a low to high transition. If TE is high, the counter will increment each time
TMR receives a high to low transition. As in the case of the other two modes, when the counter is
full, the timer will overflow and generate an internal interrupt signal; the counter will preload the
value already loaded into the preload register. To ensure that the external pin PC1/TMR is config-
ured to operate as an event counter input pin, two things have to happen. The first is to ensure that
the TM0 and TM1 bits place the timer/event counter in the event counting mode, the second is to
ensure that the port control register configures the pin as an input. It should be noted that a timer
overflow is one of the interrupt and wake-up sources.
Configuring the Pulse Width Measurement Mode
In this mode, the width of external pulses applied to the pin-shared external pin PC1/TMR can be
measured. In the Pulse Width Measurement Mode, the timer clock source is supplied by the inter-
nal clock. For the timer to operate in this mode, bits TM0 and TM1 must both be set high. If the TE
bit is low, once a high to low transition has been received on the PC1/TMR pin, the timer will start
counting until the PC1/TMR pin returns to its original high level. At this point the TON bit will be au-
tomatically reset to zero and the timer will stop counting. If the TE bit is high, the timer will begin
counting once a low to high transition has been received on the PC1/TMR pin and stop counting
when the PC1/TMR pin returns to its original low level. As before, the TON bit will be automatically
reset to zero and the timer will stop counting. It is important to note that in the Pulse Width Mea-
surement Mode, the TON bit is automatically reset to zero when the external control signal on the
external timer pin returns to its original level, whereas in the other two modes the TON bit can only
be reset to zero under program control. The residual value in the timer, which can now be read by
the program, therefore represents the length of the pulse received on pin PC1/TMR. As the TON
bit has now been reset any further transitions on the PC1/TMR pin will be ignored. Not until the
TON bit is again set high by the program can the timer begin further pulse width measurements. In
this way single shot pulse measurements can be easily made. It should be noted that in this mode
the counter is controlled by logical transitions on the PC1/TMR pin and not by the logic level. As in
the case of the other two modes, when the counter is full, the timer will overflow and generate an in-
ternal interrupt signal. The counter will also be reset to the value already loaded into the preload
register. To ensure that the external pin PC1/TMR is configured to operate as a pulse width mea-
suring input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place
the timer/event counter in the pulse width measuring mode, the second is to ensure that the port
control register configures the pin as an input. It should be noted that a timer overflow is one of the
interrupt and wake-up sources.
Chapter 1 Hardware Structure
29
T i m e r + 2 T i m e r + 3
E x t e r n a l E v e n t
I n c r e m e n t
T i m e r C o u n t e r
T i m e r + 1
Event Counter Mode Timing Chart