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Holtek HT48CA5, Техническая документация

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HT48RA5/HT48CA5

Remote Type 8-Bit MCU

Rev. 1.40

1

May 22, 2009

General Description

The HT48RA5/HT48CA5 are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for multiple I/O control product applications.
The data ROM can be used to store remote control
codes. The mask version HT48CA5 is fully pin and func-
tionally compatible with the OTP version HT48RA5 de-
vice.

The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, watchdog timer,
programmable frequency divider, HALT and wake-up
functions, as well as low cost, enhance the versatility of
these devices to suit a wide range of application possi-
bilities such as industrial control, consumer products,
subsystem controllers, and particularly suitable for use
in products such as universal remote controller (URC).

Features

·

Operating voltage: 2.0V~5.5V

·

23 bidirectional I/O lines (max.)

·

1 interrupt input shared with an I/O line

·

8-bit programmable timer/event counter with
overflow interrupt and 8-stage prescaler (TMR0)

·

16-bit programmable timer/event counter and
overflow interrupts (TMR1)

·

On-chip crystal and RC oscillator

·

Watchdog Timer

·

40K

´

16 program memory (8K

´

16 bits

´

5 banks)

·

224

´

8 data memory RAM

·

PFD supported

·

HALT function and wake-up feature reduce power
consumption

·

8-level subroutine nesting

·

Up to 1

m

s instruction cycle with 4MHz system clock at

V

DD

=3V

·

Bit manipulation instruction

·

16-bit table read instruction

·

63 powerful instructions

·

All instructions in one or two machine cycles

·

Low voltage reset function

·

28-pin SOP/SSOP (209mil) package

Technical Document

·

Tools Information

·

FAQs

·

Application Note

-

HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series

-

HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series

-

HA0041E Using the HT48CA0 to Generate the HT6221 Output Signals

-

HA0075E MCU Reset and Oscillator Circuits Application Note

-

HA0076E HT48RAx/HT48CAx Software Application Note

-

HA0082E HT48xA0-1 and HT48xA0-2 Power-on Reset Timing

Содержание HT48CA5

Страница 1: ...ax 1 interrupt input shared with an I O line 8 bit programmable timer event counter with overflow interrupt and 8 stage prescaler TMR0 16 bit programmable timer event counter and overflow interrupts TMR1 On chip crystal and RC oscillator Watchdog Timer 40K 16 program memory 8K 16 bits 5 banks 224 8 data memory RAM PFD supported HALT function and wake up feature reduce power consumption 8 level sub...

Страница 2: ... D M U X P C 0 T M R 0 T M R 0 C T M R 0 V S S P r e s c a l e r f S Y S P r o g r a m R O M P r o g r a m C o u n t e r I n t e r r u p t C i r c u i t S T A C K I N T C D A T A M e m o r y I n s t r u c t i o n R e g i s t e r M U X I n s t r u c t i o n D e c o d e r S T A T U S A L U S h i f t e r T i m i n g G e n e r a t o r A C C M U X M P W D T S W D T W D T O S C W D T P r e s c a l e r M...

Страница 3: ... pins PF0 INT I O Pull high Bidirectional 1 bit input output port Software instructions determine the CMOS output or Schmitt trigger input with without pull high resistor The pull high resis tor of this input output line is also optional PF0 is pin shared with the INT func tion pin OSC1 OSC2 I O Crystal or RC OSC1 OSC2 are connected to an RC network or Crystal determined by option for the internal...

Страница 4: ... 4 10 mA ISTB2 Standby Current WDT Disabled 3V No load system HALT 0 1 1 mA 5V 0 2 2 mA VIL1 Input Low Voltage for I O Ports 0 0 3VDD V VIH1 Input High Voltage for I O Ports 0 7VDD VDD V VIL2 Input Low Voltage RES 0 0 4VDD V VIH2 Input High Voltage RES 0 9VDD VDD V VLVR Low Voltage Reset LVR 2 0V 1 8 1 9 2 0 V LVR 3 0V 2 7 3 0 3 3 V IOL I O Port Sink Current 3V VOL 0 1VDD 4 8 mA 5V 10 20 mA IOH I ...

Страница 5: ...46 ms 5V 8 17 33 ms tWDT2 Watchdog Time out Period fSYS 4 Without WDT prescaler 1024 tSYS tRES External Reset Low Pulse Width 1 ms tSST System Start up Timer Period Power up reset or wake up from HALT 1024 tSYS tLVR Low Voltage Width to Reset 1 ms tINT Interrupt Pulse Width 1 ms Note tSYS 1 fSYS Power on Reset Characteristics Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VPOR VD...

Страница 6: ... interrupts the PC manipulates the program transfer by loading the address corresponding to each instruction The conditional skip is activated by instructions Once the condition is met the next instruction fetched during the current instruction execution is discarded and a dummy cycle replaces it to get the proper instruction Otherwise proceed to the next instruction The lower byte of the program ...

Страница 7: ... thus brought about Given this using the table read instruction in the main routine and the ISR simultaneously should be avoided However if the table read instruction has to be applied in both main routine and the ISR the in terrupt s is supposed to be disabled prior to the table read instruction It They will not be enabled until the TBLH in the main routine has been backup All table related instr...

Страница 8: ...y SET m i and CLR m i They are also indirectly accessible through memory pointer registers MP0 or MP1 Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented Any read write op eration of 00H 02H will access data memory pointed to by MP0 MP1 Reading location 00H 02H itself indi rectly will return the result 00H Writing indirectly resul...

Страница 9: ...owed by a branch to a subroutine at specified location in the pro gram memory Only the program counter is pushed onto the stack If the contents of the register or status register STATUS are altered by the interrupt service program which corrupts the desired control sequence the con tents should be saved in advance External interrupts are triggered by a high to low transi tion of the INT and the re...

Страница 10: ...m are designed for system clocks namely the RC oscillator and the crystal oscillator which are de termined by options No matter what oscillator type is selected the signal provides the system clock The HALT mode stops the system oscillator and resists the external signal to conserve power If an RC oscillator is used an external resistor between OSC1 and VSS is required and the resistance should ra...

Страница 11: ...l initialize a warm reset and only the program counter and SP are reset to zero To clear the contents of WDT including the WDT prescaler three methods are adopted external reset a low level to RES software instruction and a HALT instruction The software instruction include CLR WDT and the other set CLR WDT1 and CLR WDT2 Of these two types of instruction only one can be active depending on the ROM ...

Страница 12: ...warm re set that resets only the program counter and SP leav ing the other circuits in their original state Some regis ters remain unchanged during other reset conditions Most registers are reset to the initial condition when the reset conditions are met By examining the PDF and TO flags the program can distinguish between different chip resets TO PDF RESET Conditions 0 0 RES reset during power up...

Страница 13: ... uuuu uuuu WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu STATUS 00 xxxx 1u uuuu uu uuuu 01 uuuu 11 uuuu INTC 000 0000 000 0000 000 0000 000 0000 uuu uuuu TMR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C 00 0 1000 00 0 1000 00 0 1000 00 0 1000 uu u uuuu TMR1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 00 0 1 0...

Страница 14: ...nal level and reset the T0ON The measured result will remain in the Timer Event Counter 0 even if the acti vated transition occurs again In other words only one cycle measurement can be done Until setting the T0ON the cycle measurement will function again as long as it receives further transition pulse Note that in this operating mode the Timer Event Counter 0 starts counting not according to the ...

Страница 15: ...ter 1 even if the acti vated transition occurs again In other words only one cycle measurement can be done Until setting the T1ON the cycle measurement will function again as long as it receives further transition pulse Note that in this operating mode the Timer Event Counter 1 starts counting not according to the logic level but according to the transition edges In the case of counter overflows t...

Страница 16: ...tten Each I O line has its own control register PAC PBC PCC PFC to control the input output configuration With this control register CMOS output or Schmitt trig ger input with or without depends on options pull high resistor structures can be reconfigured dynamically i e on the fly under software control To function as an in put the corresponding latch of the control register has to be set as 1 Th...

Страница 17: ...ption x PB0 PFD PFD PB0 14H Bit0 x D 0 1 PB0 Pad Status I D 0 PFD Note I Input O Output D Data Bank Pointer There is a bank pointer used to control the program flow to go to any banks A bank contains 8K 16 address space The contents of bank pointer are load into pro gram counter when the JMP or CALL instruction is exe cuted The program counter is a 16 bit register whose contents are used to specif...

Страница 18: ...PFD CLR WDT instructions System oscillators RC or crystal WDT enable or disable WDT clock source WDTOSC or system clock 4 LVR function enable or disable LVR voltage 2 0V or 3 0V V D D 5 5 V V L V R 0 9 V 0 V R e s e t S i g n a l R e s e t 1 2 N o r m a l O p e r a t i o n R e s e t L V R D e t e c t V o l t a g e Low Voltage Reset Note 1 To make sure that the system oscillator has stabilized the ...

Страница 19: ... mains within its operating voltage range before the RES pin reaches a high level Ensure that the length of the wiring connected to the RES pin is kept as short as possible to avoid noise interference 3 For applications where noise may interfere with the reset circuit and for details on the oscillator external components refer to Application Note HA0075E for more information HT48RA5 HT48CA5 Rev 1 ...

Страница 20: ... D R e s e t C i r c u i t V D D P B 0 P F D 2 2 0 W 1 k W 1 0 0 m F 3 3 W 1 W O S C 1 O S C 2 O S C C i r c u i t V b a t P A 0 P A 1 P A 2 P A 3 P A 4 P A 5 P A 6 P A 7 P B 2 P B 3 P B 4 P B 5 P B 6 P B 7 P C 0 T M R 0 P C 1 P F 0 I N T L e a r n i n g I n p u t P C 2 P C 3 P C 4 P C 5 T M R 1 R e c e i v e r E E P R O M ...

Страница 21: ...of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out Care must be taken to en sure correct handling of carry and borrow data when re sults exceed 255 for addition and less than 0 for subtraction The increment and decrement instructions INC INCA DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destinatio...

Страница 22: ...ctions Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be con sulted as a basic instruction reference using the follow ing listed conventions Table conventions x Bits immediate data m Data Memory address A Accumulator i 0 7 number of bits addr Program memory address Mnemonic Description Cycles Flag Affected Arithmetic A...

Страница 23: ...ro with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Table Read TABRDC m TABRDL m Read table current page to TBLH and Data Memory Read t...

Страница 24: ...t is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform ...

Страница 25: ...s None CLR WDT Clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in conjunc tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect Re petitively executing this instru...

Страница 26: ... or if the C flag is set then a value of 6 will be added to the high nibble Essentially the decimal conversion is performed by add ing 00H 06H 60H or 66H depending on the Accumulator and flag conditions Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H o...

Страница 27: ...addr Affected flag s None MOV A m Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator Operation ACC m Affected flag s None MOV A x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator Operation ACC x Affected flag s None MOV m A Move ACC to Data Memory Description The contents of the Accumulator a...

Страница 28: ...continues at the restored address Operation Program Counter Stack ACC x Affected flag s None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re enabled by set ting the EMI bit EMI is the master interrupt global enable bit If an interrupt was pending when the RETI instruction is executed the pending Interrupt routine will be processed be ...

Страница 29: ...flag s None RRA m Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro tated into bit 7 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i m i 1 i 0 6 ACC 7 m 0 Affected flag s None RRC m Rotate Data Memory right through Carry Descriptio...

Страница 30: ...re first decremented by 1 If the result is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SDZA m Skip if decrement Data Memory is zero with result in ACC Descript...

Страница 31: ...hile the next instruction is fetched it is a two cycle instruction If the result is 0 the program proceeds with the following instruction Operation Skip if m i 0 Affected flag s None SUB A m Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator The result is stored in the Accumulator Note that if the result of subtraction is negative...

Страница 32: ...this requires the insertion of a dummy instruc tion while the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation ACC m Skip if m 0 Affected flag s None SZ m i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0 the following instruction is skipped As this re quires the i...

Страница 33: ...mory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op eration The result is stored in the Data Memory Operation m ACC XOR m Affected flag s Z XOR A x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation The result is stored in the Accumulator Operation ACC ACC...

Страница 34: ...n SOP 300mil Outline Dimensions MS 013 Symbol Dimensions in mil Min Nom Max A 393 419 B 256 300 C 12 20 C 697 713 D 104 E 50 F 4 12 G 16 50 H 8 13 a 0 8 HT48RA5 HT48CA5 Rev 1 40 34 May 22 2009 2 8 1 1 5 1 4 A B C D F C G H a E ...

Страница 35: ... Dimensions MO 150 Symbol Dimensions in mm Min Nom Max A 7 40 8 20 B 5 00 5 60 C 0 22 0 33 C 9 90 10 50 D 2 00 E 0 65 F 0 05 G 0 55 0 95 H 0 09 0 21 a 0 8 HT48RA5 HT48CA5 Rev 1 40 35 May 22 2009 2 8 1 1 5 1 4 A B C D F C G H a E ...

Страница 36: ...0 0 5 0 2 D Key Slit Width 2 0 0 5 T1 Space Between Flange 24 8 0 3 0 2 T2 Reel Thickness 30 2 0 2 SSOP 28S 209mil Symbol Description Dimensions in mm A Reel Outer Diameter 330 0 1 0 B Reel Inner Diameter 100 0 1 5 C Spindle Hole Diameter 13 0 0 5 0 2 D Key Slit Width 2 0 0 5 T1 Space Between Flange 28 4 0 3 0 2 T2 Reel Thickness 31 1 max HT48RA5 HT48CA5 Rev 1 40 36 May 22 2009 A C B T 1 T 2 D ...

Страница 37: ...e Width 21 3 0 1 SSOP 28S 209mil Symbol Description Dimensions in mm W Carrier Tape Width 24 0 0 3 P Cavity Pitch 12 0 0 1 E Perforation Position 1 75 0 10 F Cavity to Perforation Width Direction 11 5 0 1 D Perforation Diameter 1 5 0 1 0 0 D1 Cavity Hole Diameter 1 50 0 25 0 00 P0 Perforation Pitch 4 0 0 2 P1 Cavity to Perforation Length Direction 2 0 0 1 A0 Cavity Length 8 4 0 1 B0 Cavity Width 1...

Страница 38: ...heng District Beijing China 100031 Tel 86 10 6641 0030 86 10 6641 7751 86 10 6641 7752 Fax 86 10 6641 0125 Holtek Semiconductor USA Inc North America Sales Office 46729 Fremont Blvd Fremont CA 94538 Tel 1 510 252 9880 Fax 1 510 252 9885 http www holtek com Copyright Ó 2009 by HOLTEK SEMICONDUCTOR INC The information appearing in this Data Sheet is believed to be accurate at the time of publication...

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