HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41
34
December 30, 2008
Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter or an A/D converter re-
quires microcontroller attention, their corresponding in-
terrupt will enforce a temporary suspension of the main
program allowing the microcontroller to direct attention
to their respective needs. Each device in this series con-
tains a single external interrupt and two internal inter-
rupts functions. The external interrupt is controlled by
the action of the external INT pin, while the internal inter-
rupts are controlled by the Timer/Event Counter over-
flow and the A/D converter interrupt.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by a single INTC
register, which is located in Data Memory. By controlling
the appropriate enable bits in this register each individ-
ual interrupt can be enabled or disabled. Also when an
interrupt occurs, the corresponding request flag will be
set by the microcontroller. The global enable flag if
cleared to zero will disable all interrupts.
Interrupt Operation
A Timer/Event Counter overflow, an end of A/D conver-
sion or the external interrupt line being pulled low will all
generate an interrupt request by setting their corre-
sponding request flag, if their appropriate interrupt en-
able bit is set. When this happens, the Program
Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The
Program Counter will then be loaded with a new ad-
dress which will be the value of the corresponding inter-
rupt vector. The microcontroller will then fetch its next
instruction from this interrupt vector. The instruction at
this vector will usually be a JMP statement which will
jump to another section of program which is known as
the interrupt service routine. Here is located the code to
control the appropriate interrupt. The interrupt service
routine must be terminated with a RETI statement,
which retrieves the original Program Counter address
from the stack and allows the microcontroller to continue
with normal execution at the point where the interrupt
occurred.
The various interrupt enable bits, together with their as-
sociated request flags, are shown in the following dia-
gram with their order of priority.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked, as the EMI bit will be cleared au-
tomatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests oc-
cur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be re-
corded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the rou-
tine, to allow interrupt nesting. If the stack is full, the in-
terrupt request will not be acknowledged, even if the
I N T C R e g i s t e r
M a s t e r I n t e r r u p t G l o b a l E n a b l e
1 : g l o b a l e n a b l e
0 : g l o b a l d i s a b l e
F o r t e s t m o d e u s e o n l y .
M u s t b e w r i t t e n a s " 0 " o t h e r w i s e m a y
r e s u l t i n u n p r e d i c t a b l e o p e r a t i o n
b 7
b 0
E T I
E E I
E M I
T i m e r / E v e n t C o u n t e r I n t e r r u p t E n a b l e
1 : e n a b l e
0 : d i s a b l e
T i m e r / E v e n t C o u n t e r I n t e r r u p t R e q u e s t F l a g
1 : a c t i v e
0 : i n a c t i v e
E I F
T F
E A D I
A D F
A / D C o n v e r t e r I n t e r r u p t E n a b l e
1 : e n a b l e
0 : d i s a b l e
E x t e r n a l I n t e r r u p t E n a b l e
1 : e n a b l e
0 : d i s a b l e
E x t e r n a l I n t e r r u p t R e q u e s t F l a g
1 : a c t i v e
0 : i n a c t i v e
A / D C o n v e r t e r I n t e r r u p t R e q u e s t F l a g
1 : a c t i v e
0 : i n a c t i v e
Interrupt Control Register
