HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41
22
December 30, 2008
Configuring the Timer Mode
In this mode, the timer can be utilised to measure fixed
time intervals, providing an internal interrupt signal each
time the counter overflows. To operate in this mode, bits
TM1 and TM0 of the TMRC register must be set to 1 and
0 respectively. In this mode, the internal clock is used as
the timer clock. The input clock frequency to the timer is
f
SYS
divided by the value programmed into the timer
prescaler, the value of which is determined by bits
PSC0~PSC2 of the TMRC register. The timer-on bit,
TON must be set high to enable the timer to run. Each
time an internal clock high to low transition occurs, the
timer increments by one. When the timer is full and over-
flows, the timer will be reset to the value already loaded
into the preload register and continue counting. If the
timer interrupt is enabled, an interrupt signal will also be
generated. The timer interrupt can be disabled by ensur-
ing that the ETI bit in the INTC register is cleared to zero.
It should be noted that a timer overflow is one of the
wake-up sources.
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on external pin PA4/TMR, can be re-
corded by the internal timer. For the timer to operate in
the event counting mode, bits TM1 and TM0 of the
TMRC register must be set to 0 and 1 respectively. The
timer-on bit, TON must be set high to enable the timer to
count. With TE low, the counter will increment each time
the PA4/TMR pin receives a low to high transition. If the
TE bit is high, the counter will increment each time TMR
receives a high to low transition. As in the case of the
other two modes, when the counter is full and overflows,
the timer will be reset to the value already loaded into
the preload register and continue counting. If the timer
interrupt is enabled, an interrupt signal will also be gen-
erated. The timer interrupt can be disabled by ensuring
that the ETI bit in the INTC register is cleared to zero. To
ensure that the external pin PA4/TMR is configured to
operate as an event counter input pin, two things have to
happen. The first is to ensure that the TM0 and TM1 bits
place the timer/event counter in the event counting
mode, the second is to ensure that the port control regis-
ter configures the pin as an input. It should be noted that
a timer overflow is one of the wake-up sources. Also in
the Event Counting mode, the Timer/Event Counter will
continue to record externally changing logic events on
the timer input pin, even if the microcontroller is in the
Power Down Mode. As a result when the timer over-
flows it will generate a wake-up and if the interrupts are
enabled also generate a timer interrupt signal.
Configuring the Pulse Width Measurement Mode
In this mode, the width of external pulses applied to the
pin-shared external pin PA4/TMR can be measured. In
the Pulse Width Measurement Mode, the timer clock
source is supplied by the internal clock. For the timer to
operate in this mode, bits TM0 and TM1 must both be
set high. If the TE bit is low, once a high to low transition
has been received on the PA4/TMR pin, the timer will
start counting until the PA4/TMR pin returns to its origi-
nal high level. At this point the TON bit will be automati-
cally reset to zero and the timer will stop counting. If the
TE bit is high, the timer will begin counting once a low to
high transition has been received on the PA4/TMR pin
and stop counting when the PA4/TMR pin returns to its
original low level. As before, the TON bit will be automat-
ically reset to zero and the timer will stop counting. It is
important to note that in the Pulse Width Measurement
Mode, the TON bit is automatically reset to zero when
the external control signal on the external timer pin re-
turns to its original level, whereas in the other two
modes the TON bit can only be reset to zero under pro-
gram control. The residual value in the timer, which can
now be read by the program, therefore represents the
length of the pulse received on pin PA4/TMR. As the
TON bit has now been reset any further transitions on
the PA4/TMR pin will be ignored. Not until the TON bit is
again set high by the program can the timer begin fur-
ther pulse width measurements. In this way single shot
pulse measurements can be easily made. It should be
noted that in this mode the counter is controlled by logi-
cal transitions on the PA4/TMR pin and not by the logic
level.
I n c r e m e n t
T i m e r C o n t r o l l e r
P r e s c a l e r O u t p u t
T i m e r + 1
T i m e r + 2
T i m e r + N
T i m e r + N + 1
Timer Mode Timing Chart
T i m e r + 2
E x t e r n a l E v e n t
I n c r e m e n t
T i m e r C o u n t e r
T i m e r + 3
T i m e r + 1
Event Counter Mode Timing Chart
