Control Register Operating Mode
Select Bits for the Timer Mode
Bit7
Bit6
1
0
In this mode the internal clock is used as the timer clock. The timer input clock source is either the
f
SYS
/4 or the LIRC oscillator. The timer-on bit, T1ON must be set high to enable the timer to run. Each
time an internal clock high to low transition occurs, the timer increments by one; when the timer is full
and overflows, an interrupt signal is generated and the timer will reload the value already loaded into
the preload register and continue counting. A timer overflow condition and corresponding internal
interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring
that the ET1I bits of the INTC3 register are reset to zero.
Event Counter Mode
In this mode, a number of externally changing logic events, occurring on the external timer TC1 pin,
can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit
pair, T1M1/T1M0, in the Timer Control Register must be set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Event Counter Mode
Bit7
Bit6
0
1
In this mode, the external timer TC1 pin is used as the Timer/Event Counter clock source. After the
other bits in the Timer Control Register have been setup, the enable bit T1ON, which is bit 4 of the
Timer Control Register, can be set high to enable the Timer/Event Counter to run. If the Active Edge
Select bit, T1EG, which is bit 3 of the Timer Control Register, is low, the Timer/Event Counter will
increment each time the external timer pin receives a low to high transition. If the T1EG is high, the
counter will increment each time the external timer pin receives a high to low transition. When it is full
and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value
already loaded into the preload register and continue counting. The interrupt can be disabled by
ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control
Register is reset to zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an
event counter input pin, two things have to happen. The first is to ensure that the Operating Mode
Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting Mode,
the second is to ensure that the port control register configures the pin as an input. It should be noted
that in the event counting mode, even if the microcontroller is in the Idle/Sleep Mode, the Timer/Event
Counter will continue to record externally changing logic events on the timer input TC1 pin. As a
result when the timer overflows it will generate a timer interrupt and corresponding wake-up source.
BS83B08-3/B12-3/B16-3/B16G-3/C24-3
8-Bit Touch Key Flash MCU
Rev. 1.50
71
April 28, 2020
T i m e r + 2
E x t e r n a l E v e n t
I n c r e m e n t
T i m e r C o u n t e r
T i m e r + 3
T i m e r + 1
Event Counter Mode Timing Chart (T1EG=1)
I n c r e m e n t
T i m e r C o n t r o l l e r
P r e s c a l e r O u t p u t
T i m e r + 1
T i m e r + 2
T i m e r + N
T i m e r + N + 1
Time Mode Timing Chart
