Reading Data from the EEPROM
To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high
to enable the read function. The EEPROM address of the data to be read must then be placed in the
EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the
RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle
terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the
EED register. The data will remain in the EED register until another read or write operation is
executed. The application program can poll the RD bit to determine when the data is valid for reading.
Writing Data to the EEPROM
The EEPROM address of the data to be written must first be placed in the EEA register and the data
placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC
register must first be set high to enable the write function. After this, the WR bit in the EEC register
must be immediately set high to initiate a write cycle. These two instructions must be executed
consecutively. The global interrupt bit EMI should also first be cleared before implementing any write
operations, and then set again after the write cycle has started. Note that setting the WR bit high will
not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled
using an internal timer whose operation is asynchronous to microcontroller system clock, a certain
time will elapse before the data will have been written into the EEPROM. Detecting when the write
cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the
EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero
by the microcontroller, informing the user that the data has been written to the EEPROM. The
application program can therefore poll the WR bit to determine when the write cycle has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered-on the Write Enable bit in the control register will be cleared preventing any write operations.
Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0
will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of
protection against spurious write operations. During normal program operation, ensuring that the
Write Enable bit in the control register is cleared will safeguard against incorrect write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as the
EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt
enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its
associated multi-function interrupt request flag will both be set. If the global, EEPROM and
Multi-function interrupts are enabled and the stack is not full, a jump to the associated Multi-function
Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag
will be automatically reset, the EEPROM interrupt flag must be manually reset by the application
program. More details can be obtained in the Interrupt section.
Rev. 1.50
34
April 28, 2020
BS83B08-3/B12-3/B16-3/B16G-3/C24-3
8-Bit Touch Key Flash MCU
