Holtek BS82B12A-3, Руководство пользователя

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BS82B12A-3/BS82C16A-3/BS82D20A-3
Touch Key 8-Bit Flash MCU with LED/LCD Driver
BS82B12A-3/BS82C16A-3/BS82D20A-3
Touch Key 8-Bit Flash MCU with LED/LCD Driver
Timer/counter Mode
U nused
These two bits are used to determine how the CTM0 output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the CTM0 is running.
In the Compare Match Output Mode, the CT0IO1 and CT0IO0 bits determine how the
CTM0 output pin changes state when a compare match occurs from the Comparator A.
The CTM0 output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the CTM0
output pin should be setup using the CT0OC bit in the CTM0C1 register. Note that
the output level requested by the CT0IO1 and CT0IO0 bits must be different from the
initial value setup using the CT0OC bit otherwise no change will occur on the CTM0
output pin when a compare match occurs. After the CTM0 output pin changes state
it can be reset to its initial level by changing the level of the CT0ON bit from low to
high. In the PWM Mode, the CT0IO1 and CT0IO0 bits determine how the CTM0
output pin changes state when a certain compare match condition occurs. The PWM
output function is modified by changing these two bits. It is necessary to only change
the values of the CT0IO1 and CT0IO0 bits only after the CTM0 has been switched off.
Unpredictable PWM outputs will occur if the CT0IO1 and CT0IO0 bits are changed
when The CTM0 is running.
Bit 3 CT0OC : TP0 Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode
0: Active low
1: Active high
This is the output control bit for the CTM0 output pin. Its operation depends upon
whether CTM0 is being used in the Compare Match Output Mode or in the PWM
Mode. It has no effect if the CTM0 is in the Timer/Counter Mode. In the Compare
Match Output Mode it determines the logic level of the CTM0 output pin before a
compare match occurs. In the PWM Mode it determines if the PWM signal is active
high or active low.
Bit 2 CT0POL : TP0 Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the CTM0 output pin. When the bit is set high the
CTM0 output pin will be inverted and not inverted when the bit is zero. It has no effect
if the CTM0 is in the Timer/Counter Mode.
Bit 1 CT0DPX : CTM0 PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0 CT0CCLR : Select CTM Counter clear condition
0: CTM0 Comparatror P match
1: CTM0 Comparatror A match
This bit is used to select the method which clears the counter. Remember that the
Compact CTM0 contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the CT0CCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The CT0CCLR bit is not
used in the PWM Mode.