Rev. 1.20
12
�an�a�� 2�� 201�
Rev. 1.20
1�
�an�a�� 2�� 201�
BS82B12A-3/BS82C16A-3/BS82D20A-3
Touch Key 8-Bit Flash MCU with LED/LCD Driver
BS82B12A-3/BS82C16A-3/BS82D20A-3
Touch Key 8-Bit Flash MCU with LED/LCD Driver
Pin Name Function
OP
I/T
O/T
Description
PC2/
SSEG10/
KEY11
PC2
PCPU
ST
CMOS Gene�al p��pose I/O. Registe� enabled p�ll-�p.
SSEG10 SLCDC2
—
CMOS LCD d�ive� o�tp�t fo� LCD panel segment
KEY11
TKM2C1 NSI
—
To�ch ke� inp�t
PC�/
SSEG11/
KEY12
PC�
PCPU
ST
CMOS Gene�al p��pose I/O. Registe� enabled p�ll-�p.
SSEG11 SLCDC2
—
CMOS LCD d�ive� o�tp�t fo� LCD panel segment
KEY12
TKM2C1 NSI
—
To�ch ke� inp�t
PC4/TP1_0/
SSEG12
PC4
PCPU
ST
CMOS Gene�al p��pose I/O. Registe� enabled p�ll-�p.
TP1_0
TMPC
—
CMOS PTM0 o�tp�t
SSEG12 SLCDC2
—
CMOS LCD d�ive� o�tp�t fo� LCD panel segment
PC�/TP0_0/
SSEG1�
PC�
PCPU
ST
CMOS Gene�al p��pose I/O. Registe� enabled p�ll-�p.
TP0_0
TMPC
—
CMOS CTM0 o�tp�t
SSEG1� SLCDC2
—
CMOS LCD d�ive� o�tp�t fo� LCD panel segment
PC6/TP1_1/
SSEG14
PC6
PCPU
ST
CMOS Gene�al p��pose I/O. Registe� enabled p�ll-�p.
TP1_1
TMPC
—
CMOS PTM0 o�tp�t
SSEG14 SLCDC2
—
CMOS LCD d�ive� o�tp�t fo� LCD panel segment
PC7/TP0_1/
SSEG1�
PC7
PCPU
ST
CMOS Gene�al p��pose I/O. Registe� enabled p�ll-�p.
TP0_1
TMPC
—
CMOS CTM0 o�tp�t
SSEG1� SLCDC2
—
CMOS LCD d�ive� o�tp�t fo� LCD panel segment
VDD
VDD
—
PWR
—
Powe� s�ppl�
VSS
VSS
—
PWR
—
G�o�nd
Note: I/T: Input type;
O/T: Output type
OP: Optional by configuration option (CO) or register selection
PWR: Power;
ST
: Schmitt Trigger input
C
MOS
: CMOS output;
NMOS: NMOS output;
SCOM: SCOM output
AN: Analog input; NSI: Non-standard input
T
he PTM pin names and output pin control bits use
"1"
as their serial number, but other PTM related regiter
names or bit names use
"
0
".
BS82C16A-3
Pin Name Function
OP
I/T
O/T
Description
PA0/TCK1/
SCOM2/
ICPDA/
OCDSDA
PA0
PAWU
PAPU
ST
CMOS Gene�al p��pose I/O. Registe� enabled p�ll-�p and wake-�p.
TCK1
PTM0C0
ST
—
PTM0 clock inp�t
SCOM2 SLCDC0
—
SCOM LCD d�ive� o�tp�t fo� LCD panel common
ICPDA
—
ST
CMOS In-ci�c�it p�og�amming add�ess/data pin
OCDSDA
—
ST
CMOS On-chip deb�g s�ppo�t data/add�ess pin� fo� EV chip onl�.
PA1/SCOM0
PA1
PAWU
PAPU
ST
CMOS Gene�al p��pose I/O. Registe� enabled p�ll-�p and wake-�p.
SCOM0 SLCDC0
—
SCOM LCD d�ive� o�tp�t fo� LCD panel common
PA2/
SCOM�/
ICPCK/
OCDSCK
PA2
PAWU
PAPU
ST
CMOS Gene�al p��pose I/O. Registe� enabled p�ll-�p and wake-�p.
SCOM� SLCDC0
—
SCOM LCD d�ive� o�tp�t fo� LCD panel common
ICPCK
—
ST
—
In-ci�c�it p�og�amming clock pin
OCDSCK
—
ST
—
On-chip deb�g s�ppo�t clock pin� fo� EV chip onl�.
Содержание BS82B12A-3
Страница 33: ...Rev 1 20 33 January 23 2015 BS82B12A 3 BS82C16A 3 BS82D20A 3 Touch Key 8 Bit Flash MCU with LED LCD Driver ...
Страница 34: ...Rev 1 20 34 January 23 2015 BS82B12A 3 BS82C16A 3 BS82D20A 3 Touch Key 8 Bit Flash MCU with LED LCD Driver ...
Страница 35: ...Rev 1 20 35 January 23 2015 BS82B12A 3 BS82C16A 3 BS82D20A 3 Touch Key 8 Bit Flash MCU with LED LCD Driver ...