Hioki SM7860 Series, Инструкция по эксплуатации

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31
Communication Method
Status Byte Register (STB)
A status byte register is an 8-bit register output from the unit to the controller during serial polling. If even
one of the status byte register bits enabled by the service request enable register changes from “0” to
“1” the MSS bit becomes 1. At the same time, the RQS bit also becomes “1” and a service request is
generated.
The RQS bit is always synchronized with the service request and only read and simultaneously cleared
upon being serial polled. The MSS bit is only read by an “ ∗
STB?
” query and is not cleared until the event
is cleared by a command such as a “ ∗
CLS
” command.
Bit 7 ERR Unrecoverable error
Bit 6 RQS
MSS
Set to “1” when a service request is dispatched.
This is the logical sum of the other bits of the Status Byte Register.
Bit 5 ESB Standard Event Status (logical sum) bit
This is logical sum of the Standard Event Status Register.
Bit 4 MAV Message available
Indicates that a message is present in the output queue.
Bit 3 DSB Event Status (logical sum) bit
This is the logical sum of Event Status Register.
Bit 2 – Unused
Bit 1 – Unused
Bit 0 – Unused
Service Request Enable Register (SRER)
This register masks the Status Byte Register. Setting a bit of this register to “1” enables the corresponding
bit of the Status Byte Register to be used.
Event Register
Standard Event Status Register (SESR)
A standard event status register is an 8-bit register.
If any bit in the Standard Event Status Register is set to “1” (after masking by the Standard Event Status
Enable Register), bit 5 (ESB) of the Status Byte Register is set to “1”.
Refer to “Standard Event Status Enable Register (SESER)” (p. 32)
The standard event status register is cleared at the following times:
• When a “
∗
CLS
” command is executed
• When a “
ERR?
” command is executed
• When the device power is cycled