hilscher NXHX 4000-JTAG+, Описание устройства

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Schematic diagrams 51/70
5.6 DDR3_CHIPECC
c
a
n
b
e
le
ft
o
p
e
n
if
un
us
e
d
B
2
V
D
D
1
E
3
D
Q
L
0
A
1
V
D
D
Q
1
F
7
D
Q
L
1
F
2
D
Q
L
2
B
9
V
S
S
Q
2
F
8
D
Q
L
3
H
3
D
Q
L
4
A
8
V
D
D
Q
2
H
8
D
Q
L
5
G
2
D
Q
L
6
D
1
V
S
S
Q
3
H
7
D
Q
L
7
D
9
V
D
D
2
E
7
D
M
L
L
3
W
E
#
K
3
C
A
S
#
J3
R
A
S
#
L
2
C
S
#
M
2
B
A
0
N
8
B
A
1
L
7
A
1
0
/A
P
N
3
A
0
P
7
A
1
P
3
A
2
N
2
A
3
G
7
V
D
D
3
A
9
V
S
S
1
P
8
A
4
P
2
A
5
R
8
A
6
R
2
A
7
T
8
A
8
R
3
A
9
R
7
A
1
1
N
7
A
1
2
/B
C
#
K
9
C
K
E
K
7
C
K
#
D
3
D
M
U
B
3
V
S
S
2
D
7
D
Q
U
0
C
1
V
D
D
Q
3
C
3
D
Q
U
1
C
8
D
Q
U
2
D
8
V
S
S
Q
4
C
2
D
Q
U
3
A
7
D
Q
U
4
C
9
V
D
D
Q
4
A
2
D
Q
U
5
B
8
D
Q
U
6
E
2
V
S
S
Q
5
A
3
D
Q
U
7
E
1
V
S
S
3
F
3
D
Q
S
L
B
7
D
Q
S
U
#
D
2
V
D
D
Q
5
T
3
A
1
3
M
3
B
A
2
K
2
V
D
D
4
K
8
V
D
D
5
G
8
V
S
S
4
J2
V
S
S
5
E
9
V
D
D
Q
6
F
1
V
D
D
Q
7
H
9
V
D
D
Q
9
E
8
V
S
S
Q
6
F
9
V
S
S
Q
7
G
1
V
S
S
Q
8
G
9
V
S
S
Q
9
C
7
D
Q
S
U
G
3
D
Q
S
L
#
J7
C
K
M
8
V
R
E
F
C
A
K
1
O
D
T
T
7
A
1
4
M
7
A
1
5
/8
G
B
H
1
V
R
E
F
D
Q
H
2
V
D
D
Q
8
J8
V
S
S
6
L
8
Z
Q
M
1
V
S
S
7
M
9
V
S
S
8
N
1
V
D
D
6
N
9
V
D
D
7
P
1
V
S
S
9
P
9
V
S
S
1
0
R
1
V
D
D
8
R
9
V
D
D
9
T
1
V
S
S
1
1
T
2
R
E
S
E
T
#
T
9
V
S
S
1
2
B
1
V
S
S
Q
1
C
7
0
0
D
D
R
-S
D
R
A
M
-IS
4
3
T
R
1
6
2
5
6
A
L
1
2
5
K
B
L
I
DD R3L S DR AM 25 6M x 16 ba n ks (4 Gb)
IS
4
3
T
R
1
6
2
5
6
A
L
1
2
5
K
B
L
I
1 2
R
7
0
0
1
2
0
04 02
1 2
R
7
0
4
2
4
0
04 02
C
7
0
7
1
0
0
nF
0
4
0
2
1
6
V
C
7
0
8
1
0
0
nF
0
4
0
2
1
6
V
C
7
0
1
1
0
0
nF
0
4
0
2
1
6
V
C
7
0
2
1
0
0
nF
0
4
0
2
1
6
V
C
7
0
3
1
0
0
nF
0
4
0
2
1
6
V
C
7
0
4
2
.2
uF
X
7
R
0
8
0
5
1
6
V
C
7
0
6
1
0
0
nF
0
4
0
2
1
6
V
C
7
0
5
2
2
uF
X
7
R
1
2
0
6
1
0
V
1 2
R
7
0
3
1
k
04 02
1 2
R
7
0
2
1
k
04 02
1 2
R
7
0
1
1
k
04 02
C
7
0
9
1
nF
0
4
0
2
5
0
V
D
D
R
_
D
Q
S
4
_
N
[4
]
D
D
R
_
D
Q
S
4
[4
]
D
D
R
_
C
K
E
[4
,5
,6
] D
D
R
_
#
C
A
S
[4
,5
,6
]
D
D
R
_
#
R
A
S
[4
,5
,6
]
D
D
R
_
#
W
E
[4
,5
,6
]
D
D
R
_
#
C
S
[4
,5
,6
]
D
D
R
_
B
A
0
[4
,5
,6
]
D
D
R
_
B
A
1
[4
,5
,6
]
D
D
R
_
B
A
2
[4
,5
,6
] D
D
R
_
O
D
T
[4
,5
,6
]
D
D
R
_
R
S
T
[4
,5
,6
]
D
D
R
_
D
M
4
[4
]
D
D
R
_
C
K
2
[4
]
D
D
R
_
C
K
2
_
N
[4
]
D
D
R
_
C
K
2
D
D
R
_
C
K
2
_
N
D
D
R
_
A
[0
0
:1
5
]
[4
,5
,6
]
D
D
R
_
A
0
0
D
D
R
_
A
0
1
D
D
R
_
A
0
2
D
D
R
_
A
0
3
D
D
R
_
A
0
4
D
D
R
_
A
0
5
D
D
R
_
A
0
6
D
D
R
_
A
0
7
D
D
R
_
A
0
8
D
D
R
_
A
0
9
D
D
R
_
A
1
0
D
D
R
_
A
1
1
D
D
R
_
A
1
2
D
D
R
_
A
1
3
D
D
R
_
A
1
4
D
D
R
_
A
1
5
D
D
R
_
E
C
C
[0
:7
]
[4
]
D
D
R
_
E
C
C
0
D
D
R
_
E
C
C
1
D
D
R
_
E
C
C
2
D
D
R
_
E
C
C
3
D
D
R
_
E
C
C
4
D
D
R
_
E
C
C
5
D
D
R
_
E
C
C
6
D
D
R
_
E
C
C
7
G
N
D
G
N
D
G
N
D
D
D
R
_
+
V
R
E
F
[4
,5
,6
,2
1
]
G
N
D
D
D
R
_
+
V
R
E
F
G
N
D
G
N
D
D
D
R
_
Z
Q
E
C
C
D
D
R
_
D
Q
S
U
_
U
N
U
S
E
D
D
D
R
_
D
Q
S
U
_
U
N
U
S
E
D
_
N
D
D
R
_
D
M
U
_
U
N
U
S
E
D
+
1
V
5
+
1
V
5
+
1
V
5
+
1
V
5
Figure 12: "DDR3_CHIPECC" schematic diagram
NXHX 4000-JTAG+ | Device description
DOC170703HW02EN | Revision 2 | English | 2018-10 | Released | Public © Hilscher 2018