Connectors and interfaces
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11.3.2
Characteristics of the input signal at the I / O interface
The following voltage thresholds for the low and high levels at 3.3 V and 24
V are used to indicate the behavior of the input voltage at the external I/O
interface (GPIOs 0-3) on the NANL-B500G-RE analyzer device.
If the external I/O interface is set to input and 3.3 V or 24 V logic, the
following logic levels apply:
Input
NANL-B500G-RE,
value at T = -20 ... + 55°C
Low-level
V
input
= 3.3 V
0.9 V
V
input
= 24 V
6.5 V
High-level
V
input
= 3.3 V
2.3 V
V
input
= 24 V
16.7 V
Table 25: Low and High Voltage Thresholds for NANL-B500G-RE
·
Below the mentioned voltage thresholds, the input is interpreted as
"low", i. e. logic "zero".
·
Above the voltage thresholds mentioned above, the input is interpreted
as guaranteed "high", i. e. logic "one".
Important:
The voltage range between the lower voltage threshold (low level)
and the upper voltage threshold (high level) is undefined and should
be traversed as quickly as possible.
The signal rise time must be as low as possible in order to ensure the
measuring accuracy of 10 ns, i.e. the flank slope of the input signal must
correspond to the required measuring accuracy.
Figure 30: Behavior of the input voltage, examples flank rise: left - steep (desired), right - flat
(not desired)
Figure 31: Equivalent circuit diagram NANL-B500G-RE
netANALYZER device NANL-B500G-RE | Installation, operation and hardware description
DOC091110UM26EN | Revision 26 | English | 2019-07 | Released | Public
© Hilscher 2007-2019
