6 Configuration Mode Introduction
6.9 I2C Mode
UG290-2.5.2E
78(98)
Figure 6-55 Connection Diagram for I
2
C Mode
FPGA
SCLK
DIN
Host
CLK
DOUT
Note!
The figure above shows the minimum system diagram of the I
2
C MODE. The MODE value
is set to "100". The connection for the other fixed pins is shown in Figure 6-1.
Figure 6-56 I
2
C Mode Timing
I
2
C is a serial transmission bus, which transmits data according to the
protocol shown in the figure above. Under normal status, both SDA and
SCL are at high level.
Table 6-21 I
2
C Configuration Timing Parameters
Prameter
Description
S
Startup
condition
A HIGH to LOW transition on the SDA line while SCL is
HIGH.
P
Stop condition
SDA jumps from low to high while SCL is HIGH.
ADDRESS
Address frame
A unique 7-bit or 10-bit sequence for each slave device
that identifies the slave device when the master device is
about to communicate with it.
R/W
Read/Write bit
Determines whether the master sends data to the slave (0)
or reads data from the slave (1).
ACK
ACK/NACK bit
Each frame in the message is followed by an ACK/NACK
bit, and Gowin FPGA returns 0 if correct.
DATA
Data
A data has 8bits, and the most significant bit is sent first.
All DATA on the I2C bus is transmitted in 8-bit bytes. Each byte sent by
the transmitter, it releases the DATA line during the clock pulse 9, and the
receiver sends back a response signal. The response signal is a valid
response bit (ACK bit) if it is low, indicating that the receiver has
successfully received the byte. The response signal is a
non-acknowledgment bit (NACK) if it is high, which generally indicates that
the receiver did not succeed in receiving the byte. The requirement for the
ACK feedback is that the receiver pulls the SDA line low during the low
level prior to the 9th clock pulse and ensures a stable low level during the
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