5 Configuration Mode Introduction
5.2 JTAG Configuration
UG290-2.3E
30(87)
Figure 5-14 Process of reading SRAM
Start
Transfer
Read Instruction
(0x03)
Next address is valid
Transfer Initialize Address
Instruction (0x12)
End
Read data of one address
Y
N
Compute the
checksum(16bit)
Transfer
Config Disable Instruction
(0x3A)
Transfer
Config Enable Instruction
(0x15)
SRAM Erasure Process
When reconfiguring SRAM, the existing SRAM needs to be erased.
The flow is as follows:
1. Send the "0x15" instruction of ConfigEnable;
2. Send the "0x05" instruction of SRAM Erase;
3. Send the "0x02 " instruction of Noop;
4. Delay or Run Test 2~10ms;
5. Send the "0x09" instruction of SRAM Erase Done;
6. Send the "0x3A" instruction of ConfigDisabled;
