3 Development Board Circuit
3.2 Download
DBUG405-1.0E
10(25)
3.2.2
USB Download Circuit
Figure 3-1 Connection Diagram for FPGA USB Downloading
TMS_LQ144
TCK_LQ144
TDI_LQ144
TDO_LQ144
USB-to-JTAG
Chip
USB_D+
USB_D-
14
13
16
18
U9
U4
GW2AR-
LV18EQ144PC8I7
3.2.3
Download Flow
1.
FPGA SRAM Download Mode:
Plug the USB cable to the USB interface (J26) on the development
board. Power on. Open the Programmer, select SRAM mode, and then
select the bitstream file you required.
2.
FPGA MSPI Download Mode:
Plug the USB cable to the USB interface (J26) on the development
board. Set J13 to "0", and set J9 and J10 to "1". Power on. Open the
Programmer, select External Flash mode, and then select the bitstream
file you required. Turn off the power after downloading. Set J13, J9,
and J10 to "0", power on, and then the device will import the bitstream
file to SRAM from the external Flash.
3.2.4
Pinout
Table 3-1 FPGA Download and Pinout
Signal Name
Pin No.
BANK
Description
I/O
TMS
13
2
JTAG Signal
1.8V
TCK
14
2
JTAG Signal
1.8V
TDI
16
2
JTAG Signal
1.8V
TDO
18
2
JTAG Signal
1.8V
MODE0
144
0
One Mode selection pin 3.3V
MODE1
142
0
One Mode selection pin 3.3V
MODE2
143
0
One Mode selection pin 3.3V
RECONFIG_N
20
3
RECONFIG_N
3.3V
DONE
21
3
One DONE indicator
3.3V
READY
22
3
READY
3.3V
