GOWIN DK_GoAI_GW1NSR-LV4CQN48PC7I6, Руководство пользователя

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3 Development Board Circuit 3.4 Clock
DBUG391-1.0E 14(20)
3.4 Clock
3.4.1 Overview
The development board provides a 27MHz crystal oscillator connected
to the PLL input pin. This can be employed as the input clock for the PLL in
FPGA. Frequency division and multiplication of PLL can provide clocks
required by users.
3.4.2 Clock
Figure 3-4 Clock
45
27MHz
F_CLK
U1
X2
GW1NSR4
3.4.3 Pinout
Table 3-3 FPGA Clock and Reset Pinout
Name Pin No. BANK Description I/O Level
F_CLK 45 1 27MHz crystal oscillator input 3.3V
3.5 LED
There is one green LED in the development board and users can
display the required status through the LED. At the same time, in order to
facilitate the observation of the power supply situation, a power indicator
LED is left.
You can test the LEDs in the following ways:

When the FPGA corresponding pin output signal is logic low, the LED is
lit;

If the signal is high, LED is off.
Table 3-4 LED Pinout
Name Pin No. BANK Description I/O Level
F_LED2
10
0 LED2 3.3V