3 Development Board Circuit
3.3 Power Supply
DBUG391-1.0E
13(20)
3.3.2
Power System Distribution
Figure 3-3 Power System Distribution
DC5V Input
PAM2306AYPA
DC-DC
2.5V
PAM2306AYPA
DC-DC
3.3V
PAM2306AYPA
DC-DC
1.8V
USB to JTAG
(
FT2232
)
FPGA
VCCO0&VCCO1
27Mhz Clock &
FPGA Reset
FPGA VCCO3
(PSRAM)
FPGA
VCCX
HDMI
FPGA
VCCO2
PAM2306AYPA
DC-DC
2.8V
FPC
PAM2306AYPA
DC-DC
1.2V
FPGA VCC
3.3.3
Pins Distribution
Table 3-2 FPGA Power Pins Distribution
Name
Pin No.
BANK
Description
I/O Level
VCCO0
5
0
I/O Bank Voltage
3.3V
VCCO1
38
1
I/O Bank Voltage
3.3V
VCCO2
36
2
I/O Bank Voltage
2.5V
VCCO3
12, 24
3
I/O Bank Voltage
1.8V
VCCX
25
-
Auxiliary voltage
2.5V
VCC
11, 37
-
Core voltage
1.2V
VSS
26
-
GND
-
Содержание DK_GoAI_GW1NSR-LV4CQN48PC7I6
Страница 1: ...DK_GoAI_GW1NSR LV4CQN48PC7I6_V2 2 User Guide DBUG391 1 0E 03 03 2021 ...
Страница 3: ...Revision History Date Version Description 03 03 2021 1 0E Initial version published ...
Страница 27: ...5 Gowin Software DBUG391 1 0E 20 20 5 Gowin Software See SUG100 Gowin Software User Guide for details ...
Страница 28: ......