3 Development Board Circuit
3.9 MIPI/LVDS
DBUG388-1.0E
19(22)
Table 3-8 J16 FPGA Pin Distribution
Signal Name
Pin No.
Socket Pin No.
BANK
Description
I/O Level
F_LVDS_B1_P
48
1
1
Differential input
channel 1+
2.5V / 1.2V
(LVDS/MIPI)
F_LVDS_B1_N
47
2
1
Differential input
channel 1-
2.5V / 1.2V
(LVDS/MIPI)
GND
-
3
-
-
-
GND
-
4
-
-
-
F_LVDS_B2_P
46
5
1
Differential input
channel 2+
2.5V / 1.2V
(LVDS/MIPI)
F_LVDS_B2_N
45
6
1
Differential input
channel 2-
2.5V / 1.2V
(LVDS/MIPI)
GND
-
7
-
-
-
GND
-
8
-
-
-
F_LVDS_B3_P
44
9
1
Differential input
channel 3+
2.5V / 1.2V
(LVDS/MIPI)
F_LVDS_B3_N
43
10
1
Differential input
channel 3-
2.5V / 1.2V
(LVDS/MIPI)
GND
-
11
-
-
-
GND
-
12
-
-
-
F_LVDS_B4_P
42
13
1
Differential input
channel 4+
2.5V / 1.2V
(LVDS/MIPI)
F_LVDS_B4_N
41
14
1
Differential input
channel 4-
2.5V / 1.2V
(LVDS/MIPI)
GND
-
15
-
-
-
GND
-
16
-
-
-
F_LVDS_B5_P
40
17
1
Differential input
channel 5+
2.5V / 1.2V
(LVDS/MIPI)
F_LVDS_B5_N
39
18
1
Differential input
channel 5-
2.5V / 1.2V
(LVDS/MIPI)
GND
-
19
-
-
-
GND
-
20
-
-
-