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3 Development Board Circuit 

3.4 Clock, Reset 

 

DBUG377-1.0E 

13(21) 

 

3.3.3

 

FPGA Power Pinout 

Table 3-2 FPGA Power Pinout 

Name 

Pin No. 

BANK 

Description 

I/O Level 

VCCO0 

78 

0 

I/O Bank Voltage 

2.5V 

VCCO1 

12, 67 

1 

I/O Bank Voltage 

3.3V 

VCCO2 

3, 64 

2 

I/O Bank Voltage 

1.8V 

VCCO3 

58 

3 

I/O Bank Voltage 

3.3V 

VCCO4 

44 

4 

I/O Bank Voltage 

3.3V 

VCCO5 

23 

5 

I/O Bank Voltage 

2.5V 

VCCO6 

12, 67 

6 

I/O Bank Voltage 

3.3V 

VCCO7 

3, 64 

7 

I/O Bank Voltage 

1.8V 

VCCPLLL1 

14 

- 

PLLL1 power 

1.0V 

VCCPLLR1  50 

- 

PLLR1 power 

1.0V 

VCCX 

12, 67 

- 

Auxiliary voltage 
and VCCO1, VCCO6 
are internal 
connected. 

3.3V 

VCC 

1, 22, 45, 
66 

- 

Core voltage 

1.0V 

VSS 

2, 21, 24, 
43, 46, 65, 
68 

- 

GND 

- 

3.4

 

Clock, Reset 

3.4.1

 

Overview 

The development board provides a 27MHz crystal oscillator connected 

to the PLL input pin. This can be employed as the input clock for the PLL in 

FPGA. Frequency division and multiplication of PLL can provide the clock 

required by the user. 

For easier debugging, one reset signal active-low, is added on the 

development board.   

Содержание DK-GoAI-GW2AR18QN88P

Страница 1: ...DK GoAI GW2AR18QN88P_V1 1 User Guide DBUG377 1 0E 08 17 2020 ...

Страница 2: ... identified as trademarks or service marks are the property of their respective holders as described at www gowinsemi com GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms...

Страница 3: ...Revision History Date Version Description 08 17 2020 1 0E Initial version published ...

Страница 4: ...d Feedback 3 2 Introduction 4 2 1 Overview 4 2 2 Development Kit 5 2 3 PCB Components 6 2 4 System Block Diagram 7 2 5 Features 7 2 6 Development Board Description 8 3 Development Board Circuit 10 3 1 FPGA Module 10 3 2 Download 10 3 2 1 Overview 10 3 2 2 USB Download Circuit 11 3 2 3 Download Flow 11 3 2 4 Pinout 11 3 3 Power Supply 11 3 3 1 Overview 11 3 3 2 Power System Distribution 12 3 3 3 FP...

Страница 5: ... Pinout 14 3 5 LED 14 3 5 1 Overview 14 3 5 2 LED Circuit 15 3 5 3 Pinout 15 3 6 GPIO 15 3 6 1 Overview 15 3 6 2 Pinout 16 3 7 FPC Connector 16 3 7 1 Overview 16 3 7 2 FPC Circuit 16 3 7 3 Pinout 17 3 8 HDMI 18 3 8 1 Overview 18 3 8 2 HDMI Circuit 18 3 8 3 Pinout 19 4 Notes 20 5 Gowin Software 21 ...

Страница 6: ...gure 2 2 A Development Kit 5 Figure 2 3 PCB Components 6 Figure 2 4 System Block Diagram 7 Figure 3 1 Connection Diagram for FPGA USB Download 11 Figure 3 2 Power System Distribution 12 Figure 3 3 Clock Reset Circuit 14 Figure 3 4 LED Circuit 15 Figure 3 5 FPC Circuit 16 Figure 3 6 HDMI Connection Diagram 18 ...

Страница 7: ...ions 2 Table 2 1 Development Board Description 8 Table 3 1 FPGA Download Pinout 11 Table 3 2 FPGA Power Pinout 13 Table 3 3 FPGA Clock and Reset Pinout 14 Table 3 4 LED Pinout 15 Table 3 5 GPIO Pinout 16 Table 3 6 FPC Pinout 17 Table 3 7 HDMI_TX Pinout 19 Table 3 8 HDMI_RX Pinout 19 ...

Страница 8: ...he use of the development board 4 An introduction to the usage of the FPGA development software 1 2 Supported Products The information in the guide applies to GW1N2AR series of FPGA products GW2AR 18 1 3 Related Documents You can find the related documents at www gowinsemi com 1 DS226 GW2AR series of FPGA Products Data Sheet 2 UG229 GW2AR series of FPGA Products Package and Pinout User Guide 3 UG1...

Страница 9: ...urable Function Unit CLS Configurable Logic Slice CRU Configurable Routing Unit LUT4 Four input Look up Tables LUT5 Five input Look up Tables LUT6 Six input Look up Tables LUT7 Seven input Look up Tables LUT8 Eight input Look up Tables REG Register ALU Arithmetic Logic Unit IOB IOB S SRAM Shadow Static Random Access Memory B SRAM Block Static Random Access Memory SP Single Port SDP Semi Dual Port ...

Страница 10: ...5 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly by the following ways Website www gowinsemi com E mail support gowinsemi com ...

Страница 11: ...een the GW2A series and the GW2AR series is that the GW2AR series integrates abundant memories The GW2AR series also provides high performance DSP resources high speed LVDS interfaces and abundant BSRAM resources These embedded resources in combination with a streamlined FPGA architecture with 55nm process make the GW2AR series of FPGA products suitable for high speed and low cost applications The...

Страница 12: ...s to use 2 2 Development Kit The development board kit includes the following items DK GoAI GW2AR18QN88P_V1 1 development board USB Cable Quick Start Guide Figure 2 2 A Development Kit 4 1 2 3 Gowin DK GoAI GW2AR18QN88P_V1 1 Development Board USB Cable DC5V Power Adaptor Quick Start Guide ...

Страница 13: ...6 21 2 3 PCB Components Figure 2 3 PCB Components 5V Power Outlet Power Switch FPGA HDMI RX Flash LED Camera Reset Key 3 3V 1 8V Power Supply 2 5V 1 2V Power Supply 2 8V Power Supply USB USB to JTAG Chip Crystal Oscillator HDMI TX 1 0V Power Supply ...

Страница 14: ...ector 6 LED OSC 27MHZ 1 HDMI TX 1 HDMI RX Power 1 0V 1 2V 1 8V 2 5V 2 8V 3 3V GW2AR LV18QN88P MINI USB 1 64Mbit SPI Flash FT232HL DC POWER JACK SWITCH 5V 5V 2 5 Features The features of the development board are as follows 1 FPGA QN48 package Up to 66 user I O Abundant LUT4 resources Multiple modes and capacities of B SRAM 2 FPGA Configuration Modes JTAG ...

Страница 15: ...supported 2 6 Development Board Description Table 2 1 Development Board Description No Name Functional Description Conditions Remarks 1 FPGA Core chip 2 Download USB interface JTAG and MSPI supported USB to JTAG chip integrated on board 3 Power Supply 3 3 V 2 8V 2 5V 1 8V 1 2 V 1 0V output via DC DC LDO circuit Input power 5V Provide power for FPGA download HDMI and other circuits via 5V to 3 3 V ...

Страница 16: ...l SPI flash 9 GPIO I O for user to extend and test 5 10 HDMI For design use One HDMI TX Interface and one HDMI RX Interface 11 FPC connector For camera input 24PIN FPC 12 Protection USB interface with ESD protection Power interface with inverse and over current protection HDMI interface with ESD protection USB interface with ESD protection 15kV non contact discharge and 8kV contact discharge Schot...

Страница 17: ...rmation see UG229 GW2AR Series of FPGA Products for more details 3 2 Download 3 2 1 Overview The development board provides an USB download interface The bitstream file can be downloaded to the internal SRAM or the external SPI flash as needed Note When downloaded to SRAM the bitstream file will be lost if the device is powered down and it will need to be downloaded again after power on If downloa...

Страница 18: ... board then power on Open the Programmer select External Flash mode and then select the bitstream file and FLASH you required Turn off the power after downloading Power on and then the device will import the bitstream file to SRAM from the external Flash 3 2 4 Pinout Table 3 1 FPGA Download Pinout Name Pin No BANK Description I O Level TMS 5 2 JTAG Signal 1 8V TCK 6 2 JTAG Signal 1 8V TDI 7 2 JTAG...

Страница 19: ...stribution DC5V Input PAM2306AYPA DC DC 2 5V PAM2306AYPA DC DC 3 3V PAM2306AYPA DC DC 1 8V USB to JTAG FT2232 FPGA VCCO3 VCCX VCC O1 VCCO6 27Mhzclock FPGA reset LED FPGA VCCO2 VCCO7 PSRAM HDMI HDMI FPC connector MSPI FPGA VCCO0 VCCO5 TPS7A7001 LDO 1 0V FPGA VCC VCCPLL PAM2306AYPA DC DC 2 8V FPC Connector PAM2306AYPA DC DC 1 2V FPC Connector ...

Страница 20: ...age 3 3V VCCO7 3 64 7 I O Bank Voltage 1 8V VCCPLLL1 14 PLLL1 power 1 0V VCCPLLR1 50 PLLR1 power 1 0V VCCX 12 67 Auxiliary voltage and VCCO1 VCCO6 are internal connected 3 3V VCC 1 22 45 66 Core voltage 1 0V VSS 2 21 24 43 46 65 68 GND 3 4 Clock Reset 3 4 1 Overview The development board provides a 27MHz crystal oscillator connected to the PLL input pin This can be employed as the input clock for ...

Страница 21: ...scription I O Level F_CLK 51 3 27MHz crystal oscillator input 3 3V F_RST_N 56 3 Reset Signal active low 3 3V 3 5 LED 3 5 1 Overview There are six green LEDs on the development board and users can display the required status There is one or two LEDs left to observe the power supply and HDMI hot plug Users can test the LEDs in the following ways When the FPGA corresponding pin output signal is logic...

Страница 22: ..._LED4 U9 GW2AR LV18QN88P LED11 54 F_LED5 LED12 55 F_LED6 3 5 3 Pinout Table 3 4 LED Pinout Name Pin No BANK Description I O Level F_LED1 48 3 LED2 3 3V F_LED2 49 3 LED3 3 3V F_LED3 52 3 LED4 3 3V F_LED4 53 3 LED5 3 3V F_LED5 54 3 LED11 3 3V F_LED6 55 3 LED12 3 3V 3 6 GPIO 3 6 1 Overview Five GPIOs are reserved on development board for user extension and test ...

Страница 23: ...7 FPC Connector 3 7 1 Overview To facilitate users to input camera signals to FPGA 24PIN FPC connector FH12 24S 0 5SH is reserved on the development board 3 7 2 FPC Circuit Figure 3 5 FPC Circuit FH12_24S_0 5SH U1 J5 GW2AR LV18QN88P PIXDATA3 PIXDATA4 PIXDATA5 PIXDATA6 PIXDATA7 PIXDATA8 PIXDATA9 HREF VSYNC SCL 39 40 38 20 19 17 16 15 13 18 PIXDATA2 PIXDATA1 PIXDATA0 37 41 42 SDA PIXCLK XCLK 11 10 3...

Страница 24: ...ference output 3 3V 10 SVDD Sensor array power 1 2V 11 DOVDD Digital image signal power 3 3V 12 PIXDATA9 17 6 video output channel 9 3 3V 13 XCLK 35 4 System clock input 3 3V 14 PIXDATA8 18 6 Video output channel 8 3 3V 15 GND GND 16 PIXDATA7 19 6 Video output channel 7 3 3V 17 PIXCLK 10 6 Pixel clock output 3 3V 18 PIXDATA6 20 6 Video output channel 6 3 3V 19 PIXDATA2 37 4 Video output channel 2 ...

Страница 25: ...erface are reserved 3 8 2 HDMI Circuit Figure 3 6 HDMI Connection Diagram HDMI_TX U1 J4 GW2AR LV18QN88P HDMI_TXCP HDMI_TXCN HDMI_TX0P HDMI_TX0N HDMI_TX1P HDMI_TX1N HDMI_TX2P HDMI_TX2N HDMI_SCL HDMI_SDA 25 26 27 28 29 31 32 77 76 30 HDMI_RX U1 J3 GW2AR LV18QN88P HDMI_RXCP HDMI_RXCN HDMI_RX0P HDMI_RX0N HDMI_RX1P HDMI_RX1N HDMI_RX2P HDMI_RX2N HDMI_SCL2 HDMI_SDA2 80 79 82 81 84 86 85 72 70 83 ...

Страница 26: ... 5V HDMI_TX2P 31 5 TMDS data 2 2 5V HDMI_TX2N 32 5 TMDS data 2 2 5V HDMI_SCL 77 1 DDC clock line 3 3V HDMI_SDA 76 1 DDC data line 3 3V Table 3 8 HDMI_RX Pinout Name Pin No BANK Description I O Level HDMI_RXCP 80 0 TMDS clock signal 2 5V HDMI_RXCN 79 0 TMDS clock signal 2 5V HDMI_RX0P 82 0 TMDS data 0 2 5V HDMI_RX0N 81 0 TMDS data 0 2 5V HDMI_RX1P 84 0 TMDS data 1 2 5V HDMI_RX1N 83 0 TMDS data 1 2 ...

Страница 27: ...tection 2 The PWDN interface of the camera is not connected to the GW2AR 18 device 3 For GW2AR 18 device PSRAM power supply is provided via VCCO2 7 Bank voltage 4 The MODE mode cannot be changed due to MODE interface grounding 5 The 27MHz clock is provided to GW2AR 18 device and 12MHz clock is provided to the USB to JTAG chip FT232HL ...

Страница 28: ...5 Gowin Software DBUG377 1 0E 21 21 5Gowin Software See SUG100 Gowin Software User Guide for details ...

Страница 29: ......

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