GD32VF103 User Manual
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Figure 16-7. Hardware flow control between two USARTs
USART 1
TX module
RX module
USART 2
RX module
TX module
TX
RX
nCTS
nRTS
RX
TX
nRTS
nCTS
RTS flow control
The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When
data frame is received, the nRTS signal goes high to prevent the transmitter from sending
next frame. The nRTS signal keeps high when the receive buffer is full, and can be cleared
by reading the USART_DATA register.
CTS flow control
The USART transmitter monitors the nCTS input pin to decide whether a data frame can be
transmitted. If the TBE bit in USART_STAT is
‘
0
’
and the nCTS signal is low, the transmitter
transmits the data frame. When the nCTS signal goes high during a transmission, the
transmitter stops after the current transmission is accomplished.
Figure 16-8. Hardware flow control
nCTS
RX
nRTS
RTS flow control
CTS flow control
TX
start
data 2
start
data 3
stop
stop
data 1
stop
start
data 1
start
data 2
stop
stop
USART_DAT
A
data 2
empty
empty
data 3
empty
idle
idle
idle
idle
If the CTS flow control is enabled, the CTSF bit in USART_STAT is set when the nCTS pin
toggles. An interrupt is generated if the CTSIE bit in USART_CTL2 is set.
16.3.7.
Multi-processor communication
In multiprocessor communication, several USARTs are connected as a network. It will be a