GigaDevice Semiconductor GD32F20 Series, Руководство пользователя

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GD32F20x User Manual
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SD
NE
NR
AS
NC
AS
SD
NW
E
A[n] A[10] A[m] Command
L H L L Bank L Col Burst write to current row
L H L L Bank H Col Burst write to current row, precharge when done
L L H H Bank Row Row Active, open row for read/write
L L H L Bank L X Precharge, close current row of the selected bank
L L H L X H X Precharge all, close current row of all banks
L L L H X X X
Auto-refresh when SDCKE = 1
Self-refresh when SDCKE = 0
L L L L L Mode Mode Load mode register
SDRAM controller operation sequence
IO configuration
SDRAMC IO port must be configured first to interface with external SDRAM, otherwise it is
left as general purpose IOs, and could be utilized by other modules. IO ports related to
SDRAM operations are summarized in the following table.
Table 25-22. IO definition of SDRAM controller
Signal Direction Description
EXMC_SDCLK O SDRAM memory clock
EXMC_SDCKE[0] O Clock enable for SDRAM memory 0
EXMC_SDCKE[1] O Clock enable for SDRAM memory 1
EXMC_SDNE[0] O Chip select for SDRAM memory 0, active low
EXMC_SDNE [1] O Chip select for SDRAM memory 1, active low
EXMC_NRAS O Row address strobe, active low
EXMC_NCAS O Column address strobe, active low
EXMC_SDNWE O Write enable, active low
EXMC_A[12:0] O Address
EXMC_A[15:14] O Bank address
EXMC_D[31:0] I/O Read/Write Data
EXMC_NBL[1:0] O Write data mask, the Low byte lane is accessed
Controller initialization
Users should follow procedure to initialize the SDRAM controller, the initialization sequence
could be applied to a single SDRAM, or two SDRAM simultaneously. This choice is made by
the device selection bits DS0 and DS1 in EXMC_SDCMD register. Initialization sequence
must be performed before any read/write memory access, otherwise, EXMC’s behavior is not
guaranteed.
1. Control parameter specification: SDRAM control register EXMC_SDCTLx should be
programed first to specify the external memory dimension, clock configuration, and
read/write strategy.