User Manual
GD32103E-EVAL
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4.9
SPI-Serial Flash
Figure 9. Schematic diagram of SPI-Serial Flash function
CS
1
SO
2
WP
3
GND
4
SI
5
SCLK
6
HOLD
7
VCC
8
U5
GD25Q40
+3V3
GND
SPI1_SCK
SPI1_MOSI
SPI1_MISO
SPIFlash_CS
SPI Flash
PE3
SPI1_MISO
SPIFlash_CS
R21
10K
Ω
+3V3
C32
50V/0.1uF
GND
PA6
SPI1_MOSI
PA7
SPI1_SCK
PA5
1
2
3
JP12
HEADER 3
DAC_OUT2
Short JP12(1,2) for DAC function
Short JP12(2,3) for SPI1 function
4.10 SDIO
Figure 10. Schematic diagram of SDIO function
R52
10K
Ω
R51
10K
Ω
R50
10K
Ω
R49
10K
Ω
R48
10K
Ω
R47
10K
Ω
R4610K
Ω
R45
10K
Ω
R53
10K
Ω
+3V3
+3V3
GND
GND
GND
2
4
5
6
8
9
10
11
12
1
13
14
15
16
17
18
19
7
3
JP21
MMC_SOCKET
+3V3
E9
16V/10uF,AVX
C47
50V/0.1uF
GND
PD2
PC12
PC8
PC9
PC10
PB8
PB9
PC7
SDIO_DAT3
SDIO_CMD
SDIO_CLK
SDIO_DAT0
SDIO_DAT1
SDIO_DAT2
SDIO_DAT4
SDIO_DAT5
SDIO_DAT6
SDIO_DAT7
PC11
SDIO_DAT3
SDIO_CMD
SDIO_CLK
SDIO_DAT0
SDIO_DAT1
SDIO_DAT2
SDIO_DAT4
SDIO_DAT5
SDIO_DAT6
SDIO_DAT7
PC6 is an AFIO, please refer to I2S
schematic for right config
PC6