Series 8650B Universal Power Meters
3-52
Publication 31470-001, Rev C, November 2, 2017
3.2.24.4
Operation Complete
Bit 0 of the Event Status Register is reserved for the Operation Complete (OPC) event. The Operation Complete
event occurs when the instrument receives the *OPC command and all previous commands are complete. In a
program, *OPC can be appended to a command to ensure that the instrument completes an operation. This
method can be used to drive the generation of a Service Request. If the Event Status Enable Register is set
correctly (*ESE 1), the status model logic will then cause the Event Status bit (bit 5) of the Status Byte Register to
be set. Then, if bit 5 of the Service Request Enable Register is set (*SRE 32), the status reporting structure will set
the RQS bit, thus generating a Service Request.
An alternative method of generating a Service Request is to use the *OPC? query. This query does not affect the
state of bit 0 (OPC) in the Event Status Register at anytime. When this query is performed, all pending
operations will complete, and then a "1" is placed in the output buffer of the 8650B. Therefore, the MAV bit of
the Status Byte Register will be set high. If the corresponding bit in the Service Request Enable Register is set
(*SRE 16), the status reporting structure will once again cause a Service Request to be generated.
*OPC
Syntax:
*OPC
Example:
*OPC
! SET ESR OPC BIT WHEN OPERATION IS COMPLETE
Description:
*OPC determines when an operation is completed. This command is generally used to monitor
the completion of long measurement sequences. It sets the Operation Complete bit (OPC) in
the Event Status Register upon completion of operation.
*OPC?
Syntax:
*OPC?
Example:
*OPC?
! RETURN A VALUE OF 1 AFTER OPERATION IS COMPLETE
Description:
The Operation Complete query allows synchronization between the controller and the test set
using either the Message Available bit (MAV) in the Status Byte Register, or a read of the
response to the *OPC? query.
3.2.24.5
Clear Status
*CLS
Example:
*CLS
! CLEARS THE SRQ AND STATUS BYTE REGISTERS
Description:
*CLS is the clear status command defined by IEEE 488.2. This command clears all of the
status bytes to the value 0. After a Service Request interrupt is transmitted from the 8650B to
the controller, use the *STB command to read the status byte from the 8650B. Then reset the
SRQ and use *CLS clear status command to reset the numeric status indication of the status
registers to 0 (all bits will be 0).
*CLS does not affect the settings of the status register enable masks. *CLS also clears the
output queue (takes 0.3 sec to complete this function).
Содержание 8650B Series
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