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Rev NR
location for the transmit signals (TxC, TXD, RTS), and the receive signals will use these same signals as the receive
inputs. Since signals are transmitted and received through the transceivers, this mode allows the setup to be verified
(including signal polarity) without any external connections. Since external signals could interfere with loopback
operation, all cables should be disconnected when running in external loopback mode.
An Internal Loopback Mode is also provided which loops back on the same channel internal to the board. This
provides a loopback method which does not depend on DTE/DCE mode or signal polarity. This can remove cable
transceiver and signal setup issues to aid in debugging.. If the Cable Transceivers are enabled, the transmit data will
still appear on the appropriate transmit pins (based on DTE/DCE Mode setting). The Pin Status register will not
reflect internally looped back signals, only signals to/from the transceivers.
3.9
General Purpose IO
Unused signals at the cable may be used for general purpose IO. The Pin Source and Pin Status Registers provide
for simple IO control of all the cable interface signals. For outputs, the output value is set using the appropriate field
in the Pin Source Register. All inputs can be read via the Pin Status register.
3.10
Interrupts
The SIO8BX2 has a number of interrupt sources which are passed to the host CPU via the PCI Interrupt A. Since
there is only one physical interrupt source, the interrupts pass through a number of “levels” to get multiplexed onto
this single interrupt. The interrupt originates in the PCI9056 PCI Bridge, which combines the internal PLX interrupt
sources (DMA) with the local space interrupt. The driver will typically take care of setting up and handling the
PCI9056 interrupts. The single Local Interrupt is made up of the interrupt sources described in Section 2.1.10. In
addition, the Zilog USC contains a number of interrupt sources which are combined into a single Local Interrupt.
The user should be aware that interrupts must be enabled at each level for an interrupt to occur. For example, if a
USC interrupt is used, it must be setup and enabled in the USC, enabled in the GSC Firmware Interrupt Control
Register, and enabled in the PCI9056. In addition, the interrupt must be acknowledged and/or cleared at each level
following the interrupt.
3.11
PCI DMA
The PCI DMA functionality allows data to be transferred between host memory and the SIO4BXR onboard FIFOs
with the least amount of CPU overhead. The PCI9056 bridge chip handles all PCI DMA functions, and the device
driver should handle the details of the DMA transfer. (Note: DMA refers to the transfer of Data from the on-board
FIFOs over the PCI bus. This should not be confused with the DMA mode of the USC – transfer of data between the
USC and the on-board FIFOs. This On-Board DMA is setup by the driver and should always be enabled).
There are two PCI DMA modes – Demand Mode DMA and Non-Demand Mode DMA. Demand Mode DMA
refers to data being transferred on demand. For receive, this means data will be transferred as soon as it is received
into the FIFO. Likewise, for transmit, data will be transferred to the FIFOs as long as the FIFO is not full. The
disadvantage to Demand Mode DMA is that the DMA transfers are dependent on the user data interface. If the user
data transfer is incomplete , the Demand mode DMA transfer will also stop. If a timeout occurs, there is no way to
determine the exact amount of data transferred before it was aborted.
Non-Demand Mode DMA does not check the FIFO empty/full flags before or during the data transfer – it simply
assumes there is enough available FIFO space to complete the transfer. If the transfer size is larger than the available
