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VMIVME-2533 Differential Digital Output Board
Control and Status Register (CSR)
The CSR controls the Test Mode (TM) Bits and the front panel Fail LED as shown in
Figure 1-5 below. The TM bits enable the TRI-STATE outputs of four data latches and
disables the output drivers to support Built-in-Test functions. The CSR is initialized
active upon system reset such that the outputs to the cable are disabled and the front
panel LED is illuminated.
The CSR uses only the upper nibble (bits 7 through 4) for controlling the test mode
functions. The lower nibble (bits 3 through 0) can be setup by the user via jumper JA.
These bits can define some function for the user to test in software.
The CSR also contains a board ID code register on the upper byte. Its value is 02 HEX.
This register can be used by system software to do automatic system configuration.
Figure 1-5
CSR Block Diagram
TEST BIT 1
WRITE
DS0
CSR EN
SYSTEM RESET
IDB07
IDB06
IDB05
IDB04
TEST BIT 2
FAIL LED BIT
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